📄 code.map.rpt
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; Name ; state.back ; state.uchgcode ; state.s_chgcode ; state.chos_ua ; state.su_open ; state.sa_open ; state.check ; state.s4 ; state.s3 ; state.s2 ; state.s1 ; state.ss ;
+-----------------+------------+----------------+-----------------+---------------+---------------+---------------+-------------+----------+----------+----------+----------+----------+
; state.ss ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; state.s1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 ;
; state.s2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 1 ;
; state.s3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ;
; state.s4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 1 ;
; state.check ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.sa_open ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.su_open ; 0 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.chos_ua ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.s_chgcode ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.uchgcode ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
; state.back ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ;
+-----------------+------------+----------------+-----------------+---------------+---------------+---------------+-------------+----------+----------+----------+----------+----------+
+---------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches ;
+----------------------------------------------------+---------------------+------------------------+
; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------+------------------------+
; openlock$latch ; WideOr14 ; yes ;
; s_out[0]$latch ; openlock~0 ; yes ;
; s_out[1]$latch ; openlock~0 ; yes ;
; s_out[2]$latch ; openlock~0 ; yes ;
; s_out[3]$latch ; openlock~0 ; yes ;
; Number of user-specified and inferred latches = 5 ; ; ;
+----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 133 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 66 ;
; Number of registers using Asynchronous Load ; 1 ;
; Number of registers using Clock Enable ; 98 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+---------------------------------------------------+
; Inverted Register Statistics ;
+-----------------------------------------+---------+
; Inverted Register ; Fan out ;
+-----------------------------------------+---------+
; user_code[4] ; 2 ;
; user_code[8] ; 2 ;
; user_code[0] ; 2 ;
; user_code[12] ; 2 ;
; state.ss ; 7 ;
; one_key[1] ; 13 ;
; one_key[2] ; 12 ;
; one_key[3] ; 12 ;
; admin_code[11] ; 2 ;
; admin_code[3] ; 2 ;
; admin_code[15] ; 2 ;
; admin_code[7] ; 2 ;
; Total number of inverted registers = 12 ; ;
+-----------------------------------------+---------+
+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 5:1 ; 12 bits ; 36 LEs ; 12 LEs ; 24 LEs ; Yes ; |CODE|user_code[1] ;
; 15:1 ; 2 bits ; 20 LEs ; 6 LEs ; 14 LEs ; Yes ; |CODE|chg_num[0] ;
; 5:1 ; 4 bits ; 12 LEs ; 4 LEs ; 8 LEs ; Yes ; |CODE|user_code[4] ;
; 5:1 ; 2 bits ; 6 LEs ; 2 LEs ; 4 LEs ; No ; |CODE|u_err~8 ;
; 22:1 ; 3 bits ; 42 LEs ; 30 LEs ; 12 LEs ; No ; |CODE|Selector11 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+-------------------------------------------------+
; Source assignments for Top-level Entity: |code ;
+----------------+-------+------+-----------------+
; Assignment ; Value ; From ; To ;
+----------------+-------+------+-----------------+
; POWER_UP_LEVEL ; Low ; - ; state.back ;
; POWER_UP_LEVEL ; Low ; - ; state.uchgcode ;
; POWER_UP_LEVEL ; Low ; - ; state.s_chgcode ;
; POWER_UP_LEVEL ; Low ; - ; state.chos_ua ;
; POWER_UP_LEVEL ; Low ; - ; state.su_open ;
; POWER_UP_LEVEL ; Low ; - ; state.sa_open ;
; POWER_UP_LEVEL ; Low ; - ; state.check ;
; POWER_UP_LEVEL ; Low ; - ; state.s4 ;
; POWER_UP_LEVEL ; Low ; - ; state.s3 ;
; POWER_UP_LEVEL ; Low ; - ; state.s2 ;
; POWER_UP_LEVEL ; Low ; - ; state.s1 ;
; POWER_UP_LEVEL ; High ; - ; state.ss ;
+----------------+-------+------+-----------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Fri Oct 10 10:20:02 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off code -c code
Info: Found 2 design units, including 1 entities, in source file code.vhd
Info: Found design unit 1: CODE-behave
Info: Found entity 1: CODE
Info: Found 1 design units, including 1 entities, in source file Block1.bdf
Info: Found entity 1: Block1
Info: Elaborating entity "code" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at code.vhd(182): signal "dout" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at code.vhd(226): signal "x" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at code.vhd(226): signal "y" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at code.vhd(232): signal "u_err" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at code.vhd(233): signal "state" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10631): VHDL Process Statement warning at code.vhd(230): inferring latch(es) for signal or variable "openlock", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at code.vhd(230): inferring latch(es) for signal or variable "s_out", which holds its previous value in one or more paths through the process
Warning (10492): VHDL Process Statement warning at code.vhd(246): signal "one_key" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at code.vhd(246): signal "openlock" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info (10041): Verilog HDL or VHDL info at code.vhd(230): inferred latch for "s_out[0]"
Info (10041): Verilog HDL or VHDL info at code.vhd(230): inferred latch for "s_out[1]"
Info (10041): Verilog HDL or VHDL info at code.vhd(230): inferred latch for "s_out[2]"
Info (10041): Verilog HDL or VHDL info at code.vhd(230): inferred latch for "s_out[3]"
Info (10041): Verilog HDL or VHDL info at code.vhd(230): inferred latch for "openlock"
Info: State machine "|CODE|state" contains 12 states
Info: Selected Auto state machine encoding method for state machine "|CODE|state"
Info: Encoding result for state machine "|CODE|state"
Info: Completed encoding using 12 state bits
Info: Encoded state bit "state.back"
Info: Encoded state bit "state.uchgcode"
Info: Encoded state bit "state.s_chgcode"
Info: Encoded state bit "state.chos_ua"
Info: Encoded state bit "state.su_open"
Info: Encoded state bit "state.sa_open"
Info: Encoded state bit "state.check"
Info: Encoded state bit "state.s4"
Info: Encoded state bit "state.s3"
Info: Encoded state bit "state.s2"
Info: Encoded state bit "state.s1"
Info: Encoded state bit "state.ss"
Info: State "|CODE|state.ss" uses code string "000000000000"
Info: State "|CODE|state.s1" uses code string "000000000011"
Info: State "|CODE|state.s2" uses code string "000000000101"
Info: State "|CODE|state.s3" uses code string "000000001001"
Info: State "|CODE|state.s4" uses code string "000000010001"
Info: State "|CODE|state.check" uses code string "000000100001"
Info: State "|CODE|state.sa_open" uses code string "000001000001"
Info: State "|CODE|state.su_open" uses code string "000010000001"
Info: State "|CODE|state.chos_ua" uses code string "000100000001"
Info: State "|CODE|state.s_chgcode" uses code string "001000000001"
Info: State "|CODE|state.uchgcode" uses code string "010000000001"
Info: State "|CODE|state.back" uses code string "100000000001"
Warning: Latch openlock$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal state.s1
Warning: Latch s_out[0]$latch has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal state.sa_open
Info: Registers with preset signals will power-up high
Info: Implemented 318 device resources after synthesis - the final resource count might be different
Info: Implemented 16 input pins
Info: Implemented 9 output pins
Info: Implemented 293 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 13 warnings
Info: Processing ended: Fri Oct 10 10:20:05 2008
Info: Elapsed time: 00:00:04
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