dds.map.eqn

利用FPGA的资源实现任意波形的产生

--M17L39 is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[10]~340
--operation mode is arithmetic

M17L39 = B1_PASTEP[16] $ (M17_cout[9]);

--M17_cout[10] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[10]
--operation mode is arithmetic

M17_cout[10] = CARRY(B1_PASTEP[16] # M17_cout[9]);


--B1_PASTEP[15] is PhaseAcc:inst|PASTEP[15]
--operation mode is normal

B1_PASTEP[15]_lut_out = FreDec & M14_cs_buffer[9] # !FreDec & (!M17_cs_buffer[9]);
B1_PASTEP[15] = DFFEA(B1_PASTEP[15]_lut_out, B1_EVENTCHECK, RST, , , , );

--B1L64Q is PhaseAcc:inst|PASTEP[15]~380
--operation mode is normal

B1L64Q = B1_PASTEP[15];


--B1_PAREG[15] is PhaseAcc:inst|PAREG[15]
--operation mode is normal

B1_PAREG[15]_lut_out = M11_cs_buffer[9];
B1_PAREG[15] = DFFEA(B1_PAREG[15]_lut_out, !B1_FP2, RST, , , , );

--B1L25Q is PhaseAcc:inst|PAREG[15]~78
--operation mode is normal

B1L25Q = B1_PAREG[15];


--M11_cs_buffer[8] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]
--operation mode is arithmetic

M11_cs_buffer[8] = B1_PASTEP[14] $ B1_PAREG[14] $ M11_cout[7];

--M11L37 is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]~344
--operation mode is arithmetic

M11L37 = B1_PASTEP[14] $ B1_PAREG[14] $ M11_cout[7];

--M11_cout[8] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[8]
--operation mode is arithmetic

M11_cout[8] = CARRY(B1_PASTEP[14] & (B1_PAREG[14] # M11_cout[7]) # !B1_PASTEP[14] & B1_PAREG[14] & M11_cout[7]);


--M14_cs_buffer[9] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[9]
--operation mode is arithmetic

M14_cs_buffer[9] = B1_PASTEP[15] $ (M14_cout[8]);

--M14L40 is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[9]~230
--operation mode is arithmetic

M14L40 = B1_PASTEP[15] $ (M14_cout[8]);

--M14_cout[9] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[9]
--operation mode is arithmetic

M14_cout[9] = CARRY(B1_PASTEP[15] & (M14_cout[8]));


--M17_cs_buffer[9] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[9]
--operation mode is arithmetic

M17_cs_buffer[9] = B1_PASTEP[15] $ (M17_cout[8]);

--M17L37 is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[9]~341
--operation mode is arithmetic

M17L37 = B1_PASTEP[15] $ (M17_cout[8]);

--M17_cout[9] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[9]
--operation mode is arithmetic

M17_cout[9] = CARRY(B1_PASTEP[15] # M17_cout[8]);


--B1_PASTEP[14] is PhaseAcc:inst|PASTEP[14]
--operation mode is normal

B1_PASTEP[14]_lut_out = FreDec & M14_cs_buffer[8] # !FreDec & (!M17_cs_buffer[8]);
B1_PASTEP[14] = DFFEA(B1_PASTEP[14]_lut_out, B1_EVENTCHECK, RST, , , , );

--B1L62Q is PhaseAcc:inst|PASTEP[14]~381
--operation mode is normal

B1L62Q = B1_PASTEP[14];


--B1_PAREG[14] is PhaseAcc:inst|PAREG[14]
--operation mode is normal

B1_PAREG[14]_lut_out = M11_cs_buffer[8];
B1_PAREG[14] = DFFEA(B1_PAREG[14]_lut_out, !B1_FP2, RST, , , , );

--B1L23Q is PhaseAcc:inst|PAREG[14]~79
--operation mode is normal

B1L23Q = B1_PAREG[14];


--M11_cs_buffer[7] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]
--operation mode is arithmetic

M11_cs_buffer[7] = B1_PASTEP[13] $ B1_PAREG[13] $ M11_cout[6];

--M11L35 is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~345
--operation mode is arithmetic

M11L35 = B1_PASTEP[13] $ B1_PAREG[13] $ M11_cout[6];

--M11_cout[7] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[7]
--operation mode is arithmetic

M11_cout[7] = CARRY(B1_PASTEP[13] & (B1_PAREG[13] # M11_cout[6]) # !B1_PASTEP[13] & B1_PAREG[13] & M11_cout[6]);


--M14_cs_buffer[8] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]
--operation mode is arithmetic

M14_cs_buffer[8] = B1_PASTEP[14] $ (M14_cout[7]);

--M14L38 is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]~231
--operation mode is arithmetic

M14L38 = B1_PASTEP[14] $ (M14_cout[7]);

--M14_cout[8] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[8]
--operation mode is arithmetic

M14_cout[8] = CARRY(B1_PASTEP[14] & (M14_cout[7]));


--M17_cs_buffer[8] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]
--operation mode is arithmetic

M17_cs_buffer[8] = B1_PASTEP[14] $ (M17_cout[7]);

--M17L35 is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]~342
--operation mode is arithmetic

M17L35 = B1_PASTEP[14] $ (M17_cout[7]);

--M17_cout[8] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[8]
--operation mode is arithmetic

M17_cout[8] = CARRY(B1_PASTEP[14] # M17_cout[7]);


--B1_PASTEP[13] is PhaseAcc:inst|PASTEP[13]
--operation mode is normal

B1_PASTEP[13]_lut_out = FreDec & M14_cs_buffer[7] # !FreDec & (!M17_cs_buffer[7]);
B1_PASTEP[13] = DFFEA(B1_PASTEP[13]_lut_out, B1_EVENTCHECK, RST, , , , );

--B1L60Q is PhaseAcc:inst|PASTEP[13]~382
--operation mode is normal

B1L60Q = B1_PASTEP[13];


--B1_PAREG[13] is PhaseAcc:inst|PAREG[13]
--operation mode is normal

B1_PAREG[13]_lut_out = M11_cs_buffer[7];
B1_PAREG[13] = DFFEA(B1_PAREG[13]_lut_out, !B1_FP2, RST, , , , );

--B1L21Q is PhaseAcc:inst|PAREG[13]~80
--operation mode is normal

B1L21Q = B1_PAREG[13];


--M11_cs_buffer[6] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]
--operation mode is arithmetic

M11_cs_buffer[6] = B1_PASTEP[12] $ B1_PAREG[12] $ M11_cout[5];

--M11L33 is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~346
--operation mode is arithmetic

M11L33 = B1_PASTEP[12] $ B1_PAREG[12] $ M11_cout[5];

--M11_cout[6] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[6]
--operation mode is arithmetic

M11_cout[6] = CARRY(B1_PASTEP[12] & (B1_PAREG[12] # M11_cout[5]) # !B1_PASTEP[12] & B1_PAREG[12] & M11_cout[5]);


--M14_cs_buffer[7] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]
--operation mode is arithmetic

M14_cs_buffer[7] = B1_PASTEP[13] $ (M14_cout[6]);

--M14L36 is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~232
--operation mode is arithmetic

M14L36 = B1_PASTEP[13] $ (M14_cout[6]);

--M14_cout[7] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[7]
--operation mode is arithmetic

M14_cout[7] = CARRY(B1_PASTEP[13] & (M14_cout[6]));


--M17_cs_buffer[7] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]
--operation mode is arithmetic

M17_cs_buffer[7] = B1_PASTEP[13] $ (M17_cout[6]);

--M17L33 is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~343
--operation mode is arithmetic

M17L33 = B1_PASTEP[13] $ (M17_cout[6]);

--M17_cout[7] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[7]
--operation mode is arithmetic

M17_cout[7] = CARRY(B1_PASTEP[13] # M17_cout[6]);


--B1_PASTEP[12] is PhaseAcc:inst|PASTEP[12]
--operation mode is normal

B1_PASTEP[12]_lut_out = FreDec & M14_cs_buffer[6] # !FreDec & (!M17_cs_buffer[6]);
B1_PASTEP[12] = DFFEA(B1_PASTEP[12]_lut_out, B1_EVENTCHECK, RST, , , , );

--B1L58Q is PhaseAcc:inst|PASTEP[12]~383
--operation mode is normal

B1L58Q = B1_PASTEP[12];


--B1_PAREG[12] is PhaseAcc:inst|PAREG[12]
--operation mode is normal

B1_PAREG[12]_lut_out = M11_cs_buffer[6];
B1_PAREG[12] = DFFEA(B1_PAREG[12]_lut_out, !B1_FP2, RST, , , , );

--B1L19Q is PhaseAcc:inst|PAREG[12]~81
--operation mode is normal

B1L19Q = B1_PAREG[12];


--M11_cs_buffer[5] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]
--operation mode is arithmetic

M11_cs_buffer[5] = B1_PASTEP[11] $ B1_PAREG[11] $ M11_cout[4];

--M11L31 is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~347
--operation mode is arithmetic

M11L31 = B1_PASTEP[11] $ B1_PAREG[11] $ M11_cout[4];

--M11_cout[5] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[5]
--operation mode is arithmetic

M11_cout[5] = CARRY(B1_PASTEP[11] & (B1_PAREG[11] # M11_cout[4]) # !B1_PASTEP[11] & B1_PAREG[11] & M11_cout[4]);


--M14_cs_buffer[6] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]
--operation mode is arithmetic

M14_cs_buffer[6] = B1_PASTEP[12] $ (M14_cout[5]);

--M14L34 is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~233
--operation mode is arithmetic

M14L34 = B1_PASTEP[12] $ (M14_cout[5]);

--M14_cout[6] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[6]
--operation mode is arithmetic

M14_cout[6] = CARRY(B1_PASTEP[12] & (M14_cout[5]));


--M17_cs_buffer[6] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]
--operation mode is arithmetic

M17_cs_buffer[6] = B1_PASTEP[12] $ (M17_cout[5]);

--M17L31 is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~344
--operation mode is arithmetic

M17L31 = B1_PASTEP[12] $ (M17_cout[5]);

--M17_cout[6] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[6]
--operation mode is arithmetic

M17_cout[6] = CARRY(B1_PASTEP[12] # M17_cout[5]);


--B1_PASTEP[11] is PhaseAcc:inst|PASTEP[11]
--operation mode is normal

B1_PASTEP[11]_lut_out = FreDec & M14_cs_buffer[5] # !FreDec & (!M17_cs_buffer[5]);
B1_PASTEP[11] = DFFEA(B1_PASTEP[11]_lut_out, B1_EVENTCHECK, RST, , , , );

--B1L56Q is PhaseAcc:inst|PASTEP[11]~384
--operation mode is normal

B1L56Q = B1_PASTEP[11];


--B1_PAREG[11] is PhaseAcc:inst|PAREG[11]
--operation mode is normal

B1_PAREG[11]_lut_out = M11_cs_buffer[5];
B1_PAREG[11] = DFFEA(B1_PAREG[11]_lut_out, !B1_FP2, RST, , , , );

--B1L17Q is PhaseAcc:inst|PAREG[11]~82
--operation mode is normal

B1L17Q = B1_PAREG[11];


--M11_cs_buffer[4] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]
--operation mode is arithmetic

M11_cs_buffer[4] = B1_PASTEP[10] $ B1_PAREG[10] $ M11_cout[3];

--M11L29 is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~348
--operation mode is arithmetic

M11L29 = B1_PASTEP[10] $ B1_PAREG[10] $ M11_cout[3];

--M11_cout[4] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[4]
--operation mode is arithmetic

M11_cout[4] = CARRY(B1_PASTEP[10] & (B1_PAREG[10] # M11_cout[3]) # !B1_PASTEP[10] & B1_PAREG[10] & M11_cout[3]);


--M14_cs_buffer[5] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]
--operation mode is arithmetic

M14_cs_buffer[5] = B1_PASTEP[11] $ (M14_cout[4]);

--M14L32 is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~234
--operation mode is arithmetic

M14L32 = B1_PASTEP[11] $ (M14_cout[4]);

--M14_cout[5] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[5]
--operation mode is arithmetic

M14_cout[5] = CARRY(B1_PASTEP[11] & (M14_cout[4]));


--M17_cs_buffer[5] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]
--operation mode is arithmetic

M17_cs_buffer[5] = B1_PASTEP[11] $ (M17_cout[4]);

--M17L29 is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~345
--operation mode is arithmetic

M17L29 = B1_PASTEP[11] $ (M17_cout[4]);

--M17_cout[5] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[5]
--operation mode is arithmetic

M17_cout[5] = CARRY(B1_PASTEP[11] # M17_cout[4]);


--B1_PASTEP[10] is PhaseAcc:inst|PASTEP[10]
--operation mode is normal

B1_PASTEP[10]_lut_out = FreDec & M14_cs_b