dds.map.eqn

利用FPGA的资源实现任意波形的产生

--G1L44 is PathSel:inst5|sinreg[1]~77
--operation mode is normal

G1L44 = PathSel[0] & P4_q[1];


--P2_q[1] is lpm_rom_juchi:inst2|lpm_rom:lpm_rom_component|altrom:srom|q[1]
P2_q[1]_clock_0 = B1_FP2;
P2_q[1]_clock_1 = B1_FP2;
P2_q[1]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P2_q[1]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P2_q[1] = MEMORY_SEGMENT(, , P2_q[1]_clock_0, P2_q[1]_clock_1, , , , , P2_q[1]_write_address, P2_q[1]_read_address);


--G1_juchireg[1] is PathSel:inst5|juchireg[1]
--operation mode is normal

G1_juchireg[1] = PathSel[1] & P2_q[1];

--G1L18 is PathSel:inst5|juchireg[1]~62
--operation mode is normal

G1L18 = PathSel[1] & P2_q[1];


--P2_q[0] is lpm_rom_juchi:inst2|lpm_rom:lpm_rom_component|altrom:srom|q[0]
P2_q[0]_clock_0 = B1_FP2;
P2_q[0]_clock_1 = B1_FP2;
P2_q[0]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P2_q[0]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P2_q[0] = MEMORY_SEGMENT(, , P2_q[0]_clock_0, P2_q[0]_clock_1, , , , , P2_q[0]_write_address, P2_q[0]_read_address);


--G1_juchireg[0] is PathSel:inst5|juchireg[0]
--operation mode is normal

G1_juchireg[0] = PathSel[1] & P2_q[0];

--G1L16 is PathSel:inst5|juchireg[0]~63
--operation mode is normal

G1L16 = PathSel[1] & P2_q[0];


--P4_q[0] is lpm_rom_sin:inst1|lpm_rom:lpm_rom_component|altrom:srom|q[0]
P4_q[0]_clock_0 = B1_FP2;
P4_q[0]_clock_1 = B1_FP2;
P4_q[0]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P4_q[0]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P4_q[0] = MEMORY_SEGMENT(, , P4_q[0]_clock_0, P4_q[0]_clock_1, , , , , P4_q[0]_write_address, P4_q[0]_read_address);


--G1_sinreg[0] is PathSel:inst5|sinreg[0]
--operation mode is normal

G1_sinreg[0] = PathSel[0] & P4_q[0];

--G1L42 is PathSel:inst5|sinreg[0]~78
--operation mode is normal

G1L42 = PathSel[0] & P4_q[0];


--M14_cs_buffer[12] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[12]
--operation mode is arithmetic

M14_cs_buffer[12] = B1_PASTEP[18] $ (!M14_cout[11]);

--M14L46 is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[12]~223
--operation mode is arithmetic

M14L46 = B1_PASTEP[18] $ (!M14_cout[11]);

--M14_cout[12] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[12]
--operation mode is arithmetic

M14_cout[12] = CARRY(!B1_PASTEP[18] & (M14_cout[11]));


--M17_cs_buffer[12] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[12]
--operation mode is arithmetic

M17_cs_buffer[12] = B1_PASTEP[18] $ (!M17_cout[11]);

--M17L43 is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[12]~334
--operation mode is arithmetic

M17L43 = B1_PASTEP[18] $ (!M17_cout[11]);

--M17_cout[12] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[12]
--operation mode is arithmetic

M17_cout[12] = CARRY(M17_cout[11] # !B1_PASTEP[18]);


--M14_cs_buffer[13] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[13]
--operation mode is arithmetic

M14_cs_buffer[13] = B1_PASTEP[19] $ (M14_cout[12]);

--M14L48 is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[13]~224
--operation mode is arithmetic

M14L48 = B1_PASTEP[19] $ (M14_cout[12]);

--M14_cout[13] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[13]
--operation mode is arithmetic

M14_cout[13] = CARRY(B1_PASTEP[19] & (M14_cout[12]));


--M17_cs_buffer[13] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[13]
--operation mode is arithmetic

M17_cs_buffer[13] = B1_PASTEP[19] $ (M17_cout[12]);

--M17L45 is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[13]~335
--operation mode is arithmetic

M17L45 = B1_PASTEP[19] $ (M17_cout[12]);

--M17_cout[13] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[13]
--operation mode is arithmetic

M17_cout[13] = CARRY(B1_PASTEP[19] # M17_cout[12]);


--M14_cs_buffer[14] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[14]
--operation mode is arithmetic

M14_cs_buffer[14] = B1_PASTEP[20] $ (M14_cout[13]);

--M14L50 is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[14]~225
--operation mode is arithmetic

M14L50 = B1_PASTEP[20] $ (M14_cout[13]);

--M14_cout[14] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[14]
--operation mode is arithmetic

M14_cout[14] = CARRY(B1_PASTEP[20] & (M14_cout[13]));


--M17_cs_buffer[14] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[14]
--operation mode is arithmetic

M17_cs_buffer[14] = B1_PASTEP[20] $ (M17_cout[13]);

--M17L47 is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[14]~336
--operation mode is arithmetic

M17L47 = B1_PASTEP[20] $ (M17_cout[13]);

--M17_cout[14] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[14]
--operation mode is arithmetic

M17_cout[14] = CARRY(B1_PASTEP[20] # M17_cout[13]);


--M14_cs_buffer[15] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[15]
--operation mode is arithmetic

M14_cs_buffer[15] = B1_PASTEP[21] $ (M14_cout[14]);

--M14L52 is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[15]~226
--operation mode is arithmetic

M14L52 = B1_PASTEP[21] $ (M14_cout[14]);

--M14_cout[15] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[15]
--operation mode is arithmetic

M14_cout[15] = CARRY(B1_PASTEP[21] & (M14_cout[14]));


--M17_cs_buffer[15] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[15]
--operation mode is arithmetic

M17_cs_buffer[15] = B1_PASTEP[21] $ (M17_cout[14]);

--M17L49 is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[15]~337
--operation mode is arithmetic

M17L49 = B1_PASTEP[21] $ (M17_cout[14]);

--M17_cout[15] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[15]
--operation mode is arithmetic

M17_cout[15] = CARRY(B1_PASTEP[21] # M17_cout[14]);


--M14_cs_buffer[16] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[16]
--operation mode is arithmetic

M14_cs_buffer[16] = B1_PASTEP[22] $ (M14_cout[15]);

--M14L54 is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[16]~227
--operation mode is arithmetic

M14L54 = B1_PASTEP[22] $ (M14_cout[15]);

--M14_cout[16] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[16]
--operation mode is arithmetic

M14_cout[16] = CARRY(B1_PASTEP[22] & (M14_cout[15]));


--M17_cs_buffer[16] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[16]
--operation mode is arithmetic

M17_cs_buffer[16] = B1_PASTEP[22] $ (M17_cout[15]);

--M17L51 is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[16]~338
--operation mode is arithmetic

M17L51 = B1_PASTEP[22] $ (M17_cout[15]);

--M17_cout[16] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[16]
--operation mode is arithmetic

M17_cout[16] = CARRY(B1_PASTEP[22] # M17_cout[15]);


--K5_unreg_res_node[17] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|unreg_res_node[17]
--operation mode is normal

K5_unreg_res_node[17] = M14_cout[16] $ B1_PASTEP[23];

--K5L3 is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|unreg_res_node[17]~36
--operation mode is normal

K5L3 = M14_cout[16] $ B1_PASTEP[23];


--K6_unreg_res_node[17] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|unreg_res_node[17]
--operation mode is normal

K6_unreg_res_node[17] = M17_cout[16] $ B1_PASTEP[23];

--K6L3 is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|unreg_res_node[17]~35
--operation mode is normal

K6L3 = M17_cout[16] $ B1_PASTEP[23];


--B1_PASTEP[17] is PhaseAcc:inst|PASTEP[17]
--operation mode is normal

B1_PASTEP[17]_lut_out = FreDec & M14_cs_buffer[11] # !FreDec & (!M17_cs_buffer[11]);
B1_PASTEP[17] = DFFEA(B1_PASTEP[17]_lut_out, B1_EVENTCHECK, RST, , , , );

--B1L68Q is PhaseAcc:inst|PASTEP[17]~378
--operation mode is normal

B1L68Q = B1_PASTEP[17];


--B1_PAREG[17] is PhaseAcc:inst|PAREG[17]
--operation mode is normal

B1_PAREG[17]_lut_out = M11_cs_buffer[11];
B1_PAREG[17] = DFFEA(B1_PAREG[17]_lut_out, !B1_FP2, RST, , , , );

--B1L29Q is PhaseAcc:inst|PAREG[17]~76
--operation mode is normal

B1L29Q = B1_PAREG[17];


--M11_cs_buffer[10] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[10]
--operation mode is arithmetic

M11_cs_buffer[10] = B1_PASTEP[16] $ B1_PAREG[16] $ M11_cout[9];

--M11L41 is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[10]~342
--operation mode is arithmetic

M11L41 = B1_PASTEP[16] $ B1_PAREG[16] $ M11_cout[9];

--M11_cout[10] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[10]
--operation mode is arithmetic

M11_cout[10] = CARRY(B1_PASTEP[16] & (B1_PAREG[16] # M11_cout[9]) # !B1_PASTEP[16] & B1_PAREG[16] & M11_cout[9]);


--M14_cs_buffer[11] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[11]
--operation mode is arithmetic

M14_cs_buffer[11] = B1_PASTEP[17] $ (M14_cout[10]);

--M14L44 is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[11]~228
--operation mode is arithmetic

M14L44 = B1_PASTEP[17] $ (M14_cout[10]);

--M14_cout[11] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[11]
--operation mode is arithmetic

M14_cout[11] = CARRY(B1_PASTEP[17] & (M14_cout[10]));


--M17_cs_buffer[11] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[11]
--operation mode is arithmetic

M17_cs_buffer[11] = B1_PASTEP[17] $ (M17_cout[10]);

--M17L41 is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[11]~339
--operation mode is arithmetic

M17L41 = B1_PASTEP[17] $ (M17_cout[10]);

--M17_cout[11] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[11]
--operation mode is arithmetic

M17_cout[11] = CARRY(B1_PASTEP[17] # M17_cout[10]);


--B1_PASTEP[16] is PhaseAcc:inst|PASTEP[16]
--operation mode is normal

B1_PASTEP[16]_lut_out = FreDec & M14_cs_buffer[10] # !FreDec & (!M17_cs_buffer[10]);
B1_PASTEP[16] = DFFEA(B1_PASTEP[16]_lut_out, B1_EVENTCHECK, RST, , , , );

--B1L66Q is PhaseAcc:inst|PASTEP[16]~379
--operation mode is normal

B1L66Q = B1_PASTEP[16];


--B1_PAREG[16] is PhaseAcc:inst|PAREG[16]
--operation mode is normal

B1_PAREG[16]_lut_out = M11_cs_buffer[10];
B1_PAREG[16] = DFFEA(B1_PAREG[16]_lut_out, !B1_FP2, RST, , , , );

--B1L27Q is PhaseAcc:inst|PAREG[16]~77
--operation mode is normal

B1L27Q = B1_PAREG[16];


--M11_cs_buffer[9] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[9]
--operation mode is arithmetic

M11_cs_buffer[9] = B1_PASTEP[15] $ B1_PAREG[15] $ M11_cout[8];

--M11L39 is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[9]~343
--operation mode is arithmetic

M11L39 = B1_PASTEP[15] $ B1_PAREG[15] $ M11_cout[8];

--M11_cout[9] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[9]
--operation mode is arithmetic

M11_cout[9] = CARRY(B1_PASTEP[15] & (B1_PAREG[15] # M11_cout[8]) # !B1_PASTEP[15] & B1_PAREG[15] & M11_cout[8]);


--M14_cs_buffer[10] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[10]
--operation mode is arithmetic

M14_cs_buffer[10] = B1_PASTEP[16] $ (M14_cout[9]);

--M14L42 is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[10]~229
--operation mode is arithmetic

M14L42 = B1_PASTEP[16] $ (M14_cout[9]);

--M14_cout[10] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[10]
--operation mode is arithmetic

M14_cout[10] = CARRY(B1_PASTEP[16] & (M14_cout[9]));


--M17_cs_buffer[10] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[10]
--operation mode is arithmetic

M17_cs_buffer[10] = B1_PASTEP[16] $ (M17_cout[9]);