dds.map.eqn

利用FPGA的资源实现任意波形的产生

B1L80Q = B1_PASTEP[23];


--K4_unreg_res_node[17] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|unreg_res_node[17]
--operation mode is normal

K4_unreg_res_node[17] = B1_PASTEP[23] $ B1_PAREG[23] $ M11_cout[16];

--K4L3 is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|unreg_res_node[17]~53
--operation mode is normal

K4L3 = B1_PASTEP[23] $ B1_PAREG[23] $ M11_cout[16];


--M2L17 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~111
--operation mode is normal

M2L17 = G1_sinreg[4] $ G1_juchireg[4] $ M2L14;

--M2L19 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~149
--operation mode is normal

M2L19 = G1_sinreg[4] $ G1_juchireg[4] $ M2L14;


--M2L18 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~115
--operation mode is normal

M2L18 = G1_sinreg[4] & (G1_juchireg[4] # M2L14) # !G1_sinreg[4] & G1_juchireg[4] & M2L14;

--M2L20 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~150
--operation mode is normal

M2L20 = G1_sinreg[4] & (G1_juchireg[4] # M2L14) # !G1_sinreg[4] & G1_juchireg[4] & M2L14;


--M2L13 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~119
--operation mode is normal

M2L13 = G1_sinreg[3] $ G1_juchireg[3] $ M2L10;

--M2L15 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~151
--operation mode is normal

M2L15 = G1_sinreg[3] $ G1_juchireg[3] $ M2L10;


--M2L14 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~123
--operation mode is normal

M2L14 = G1_sinreg[3] & (G1_juchireg[3] # M2L10) # !G1_sinreg[3] & G1_juchireg[3] & M2L10;

--M2L16 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~152
--operation mode is normal

M2L16 = G1_sinreg[3] & (G1_juchireg[3] # M2L10) # !G1_sinreg[3] & G1_juchireg[3] & M2L10;


--M2L9 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~127
--operation mode is normal

M2L9 = G1_sinreg[2] $ G1_juchireg[2] $ M2L6;

--M2L11 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~153
--operation mode is normal

M2L11 = G1_sinreg[2] $ G1_juchireg[2] $ M2L6;


--M2L10 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~131
--operation mode is normal

M2L10 = G1_sinreg[2] & (G1_juchireg[2] # M2L6) # !G1_sinreg[2] & G1_juchireg[2] & M2L6;

--M2L12 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~154
--operation mode is normal

M2L12 = G1_sinreg[2] & (G1_juchireg[2] # M2L6) # !G1_sinreg[2] & G1_juchireg[2] & M2L6;


--M2L5 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~135
--operation mode is normal

M2L5 = G1_sinreg[1] $ G1_juchireg[1] $ M2L2;

--M2L7 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~155
--operation mode is normal

M2L7 = G1_sinreg[1] $ G1_juchireg[1] $ M2L2;


--M2L6 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~139
--operation mode is normal

M2L6 = G1_sinreg[1] & (G1_juchireg[1] # M2L2) # !G1_sinreg[1] & G1_juchireg[1] & M2L2;

--M2L8 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~156
--operation mode is normal

M2L8 = G1_sinreg[1] & (G1_juchireg[1] # M2L2) # !G1_sinreg[1] & G1_juchireg[1] & M2L2;


--M2L1 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~142
--operation mode is normal

M2L1 = G1_juchireg[0] $ G1_sinreg[0];

--M2L3 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~157
--operation mode is normal

M2L3 = G1_juchireg[0] $ G1_sinreg[0];


--M2L2 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~145
--operation mode is normal

M2L2 = G1_juchireg[0] & G1_sinreg[0];

--M2L4 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~158
--operation mode is normal

M2L4 = G1_juchireg[0] & G1_sinreg[0];


--P4_q[5] is lpm_rom_sin:inst1|lpm_rom:lpm_rom_component|altrom:srom|q[5]
P4_q[5]_clock_0 = B1_FP2;
P4_q[5]_clock_1 = B1_FP2;
P4_q[5]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P4_q[5]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P4_q[5] = MEMORY_SEGMENT(, , P4_q[5]_clock_0, P4_q[5]_clock_1, , , , , P4_q[5]_write_address, P4_q[5]_read_address);


--G1_sinreg[5] is PathSel:inst5|sinreg[5]
--operation mode is normal

G1_sinreg[5] = P4_q[5] & PathSel[0];

--G1L52 is PathSel:inst5|sinreg[5]~73
--operation mode is normal

G1L52 = P4_q[5] & PathSel[0];


--P2_q[5] is lpm_rom_juchi:inst2|lpm_rom:lpm_rom_component|altrom:srom|q[5]
P2_q[5]_clock_0 = B1_FP2;
P2_q[5]_clock_1 = B1_FP2;
P2_q[5]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P2_q[5]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P2_q[5] = MEMORY_SEGMENT(, , P2_q[5]_clock_0, P2_q[5]_clock_1, , , , , P2_q[5]_write_address, P2_q[5]_read_address);


--G1_juchireg[5] is PathSel:inst5|juchireg[5]
--operation mode is normal

G1_juchireg[5] = P2_q[5] & PathSel[1];

--G1L26 is PathSel:inst5|juchireg[5]~58
--operation mode is normal

G1L26 = P2_q[5] & PathSel[1];


--B1_PASTEP[18] is PhaseAcc:inst|PASTEP[18]
--operation mode is normal

B1_PASTEP[18]_lut_out = FreDec & !M14_cs_buffer[12] # !FreDec & (M17_cs_buffer[12]);
B1_PASTEP[18] = DFFEA(B1_PASTEP[18]_lut_out, B1_EVENTCHECK, RST, , , , );

--B1L70Q is PhaseAcc:inst|PASTEP[18]~373
--operation mode is normal

B1L70Q = B1_PASTEP[18];


--M11_cs_buffer[11] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[11]
--operation mode is arithmetic

M11_cs_buffer[11] = B1_PASTEP[17] $ B1_PAREG[17] $ M11_cout[10];

--M11L43 is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[11]~341
--operation mode is arithmetic

M11L43 = B1_PASTEP[17] $ B1_PAREG[17] $ M11_cout[10];

--M11_cout[11] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[11]
--operation mode is arithmetic

M11_cout[11] = CARRY(B1_PASTEP[17] & (B1_PAREG[17] # M11_cout[10]) # !B1_PASTEP[17] & B1_PAREG[17] & M11_cout[10]);


--B1_PASTEP[19] is PhaseAcc:inst|PASTEP[19]
--operation mode is normal

B1_PASTEP[19]_lut_out = FreDec & M14_cs_buffer[13] # !FreDec & (!M17_cs_buffer[13]);
B1_PASTEP[19] = DFFEA(B1_PASTEP[19]_lut_out, B1_EVENTCHECK, RST, , , , );

--B1L72Q is PhaseAcc:inst|PASTEP[19]~374
--operation mode is normal

B1L72Q = B1_PASTEP[19];


--B1_PASTEP[20] is PhaseAcc:inst|PASTEP[20]
--operation mode is normal

B1_PASTEP[20]_lut_out = FreDec & M14_cs_buffer[14] # !FreDec & (!M17_cs_buffer[14]);
B1_PASTEP[20] = DFFEA(B1_PASTEP[20]_lut_out, B1_EVENTCHECK, RST, , , , );

--B1L74Q is PhaseAcc:inst|PASTEP[20]~375
--operation mode is normal

B1L74Q = B1_PASTEP[20];


--B1_PASTEP[21] is PhaseAcc:inst|PASTEP[21]
--operation mode is normal

B1_PASTEP[21]_lut_out = FreDec & M14_cs_buffer[15] # !FreDec & (!M17_cs_buffer[15]);
B1_PASTEP[21] = DFFEA(B1_PASTEP[21]_lut_out, B1_EVENTCHECK, RST, , , , );

--B1L76Q is PhaseAcc:inst|PASTEP[21]~376
--operation mode is normal

B1L76Q = B1_PASTEP[21];


--B1_PASTEP[22] is PhaseAcc:inst|PASTEP[22]
--operation mode is normal

B1_PASTEP[22]_lut_out = FreDec & M14_cs_buffer[16] # !FreDec & (!M17_cs_buffer[16]);
B1_PASTEP[22] = DFFEA(B1_PASTEP[22]_lut_out, B1_EVENTCHECK, RST, , , , );

--B1L78Q is PhaseAcc:inst|PASTEP[22]~377
--operation mode is normal

B1L78Q = B1_PASTEP[22];


--B1_EVENTCHECK is PhaseAcc:inst|EVENTCHECK
--operation mode is normal

B1_EVENTCHECK = !FreInc # !FreDec;

--B1L2 is PhaseAcc:inst|EVENTCHECK~7
--operation mode is normal

B1L2 = !FreInc # !FreDec;


--P4_q[4] is lpm_rom_sin:inst1|lpm_rom:lpm_rom_component|altrom:srom|q[4]
P4_q[4]_clock_0 = B1_FP2;
P4_q[4]_clock_1 = B1_FP2;
P4_q[4]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P4_q[4]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P4_q[4] = MEMORY_SEGMENT(, , P4_q[4]_clock_0, P4_q[4]_clock_1, , , , , P4_q[4]_write_address, P4_q[4]_read_address);


--G1_sinreg[4] is PathSel:inst5|sinreg[4]
--operation mode is normal

G1_sinreg[4] = PathSel[0] & P4_q[4];

--G1L50 is PathSel:inst5|sinreg[4]~74
--operation mode is normal

G1L50 = PathSel[0] & P4_q[4];


--P2_q[4] is lpm_rom_juchi:inst2|lpm_rom:lpm_rom_component|altrom:srom|q[4]
P2_q[4]_clock_0 = B1_FP2;
P2_q[4]_clock_1 = B1_FP2;
P2_q[4]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P2_q[4]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P2_q[4] = MEMORY_SEGMENT(, , P2_q[4]_clock_0, P2_q[4]_clock_1, , , , , P2_q[4]_write_address, P2_q[4]_read_address);


--G1_juchireg[4] is PathSel:inst5|juchireg[4]
--operation mode is normal

G1_juchireg[4] = PathSel[1] & P2_q[4];

--G1L24 is PathSel:inst5|juchireg[4]~59
--operation mode is normal

G1L24 = PathSel[1] & P2_q[4];


--P4_q[3] is lpm_rom_sin:inst1|lpm_rom:lpm_rom_component|altrom:srom|q[3]
P4_q[3]_clock_0 = B1_FP2;
P4_q[3]_clock_1 = B1_FP2;
P4_q[3]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P4_q[3]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P4_q[3] = MEMORY_SEGMENT(, , P4_q[3]_clock_0, P4_q[3]_clock_1, , , , , P4_q[3]_write_address, P4_q[3]_read_address);


--G1_sinreg[3] is PathSel:inst5|sinreg[3]
--operation mode is normal

G1_sinreg[3] = PathSel[0] & P4_q[3];

--G1L48 is PathSel:inst5|sinreg[3]~75
--operation mode is normal

G1L48 = PathSel[0] & P4_q[3];


--P2_q[3] is lpm_rom_juchi:inst2|lpm_rom:lpm_rom_component|altrom:srom|q[3]
P2_q[3]_clock_0 = B1_FP2;
P2_q[3]_clock_1 = B1_FP2;
P2_q[3]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P2_q[3]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P2_q[3] = MEMORY_SEGMENT(, , P2_q[3]_clock_0, P2_q[3]_clock_1, , , , , P2_q[3]_write_address, P2_q[3]_read_address);


--G1_juchireg[3] is PathSel:inst5|juchireg[3]
--operation mode is normal

G1_juchireg[3] = PathSel[1] & P2_q[3];

--G1L22 is PathSel:inst5|juchireg[3]~60
--operation mode is normal

G1L22 = PathSel[1] & P2_q[3];


--P4_q[2] is lpm_rom_sin:inst1|lpm_rom:lpm_rom_component|altrom:srom|q[2]
P4_q[2]_clock_0 = B1_FP2;
P4_q[2]_clock_1 = B1_FP2;
P4_q[2]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P4_q[2]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P4_q[2] = MEMORY_SEGMENT(, , P4_q[2]_clock_0, P4_q[2]_clock_1, , , , , P4_q[2]_write_address, P4_q[2]_read_address);


--G1_sinreg[2] is PathSel:inst5|sinreg[2]
--operation mode is normal

G1_sinreg[2] = PathSel[0] & P4_q[2];

--G1L46 is PathSel:inst5|sinreg[2]~76
--operation mode is normal

G1L46 = PathSel[0] & P4_q[2];


--P2_q[2] is lpm_rom_juchi:inst2|lpm_rom:lpm_rom_component|altrom:srom|q[2]
P2_q[2]_clock_0 = B1_FP2;
P2_q[2]_clock_1 = B1_FP2;
P2_q[2]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P2_q[2]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P2_q[2] = MEMORY_SEGMENT(, , P2_q[2]_clock_0, P2_q[2]_clock_1, , , , , P2_q[2]_write_address, P2_q[2]_read_address);


--G1_juchireg[2] is PathSel:inst5|juchireg[2]
--operation mode is normal

G1_juchireg[2] = PathSel[1] & P2_q[2];

--G1L20 is PathSel:inst5|juchireg[2]~61
--operation mode is normal

G1L20 = PathSel[1] & P2_q[2];


--P4_q[1] is lpm_rom_sin:inst1|lpm_rom:lpm_rom_component|altrom:srom|q[1]
P4_q[1]_clock_0 = B1_FP2;
P4_q[1]_clock_1 = B1_FP2;
P4_q[1]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P4_q[1]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P4_q[1] = MEMORY_SEGMENT(, , P4_q[1]_clock_0, P4_q[1]_clock_1, , , , , P4_q[1]_write_address, P4_q[1]_read_address);


--G1_sinreg[1] is PathSel:inst5|sinreg[1]
--operation mode is normal

G1_sinreg[1] = PathSel[0] & P4_q[1];