dds.map.eqn

利用FPGA的资源实现任意波形的产生

--B1L35Q is PhaseAcc:inst|PAREG[20]~72
--operation mode is normal

B1L35Q = B1_PAREG[20];


--B1_PAREG[21] is PhaseAcc:inst|PAREG[21]
--operation mode is normal

B1_PAREG[21]_lut_out = M11_cs_buffer[15];
B1_PAREG[21] = DFFEA(B1_PAREG[21]_lut_out, !B1_FP2, RST, , , , );

--B1L37Q is PhaseAcc:inst|PAREG[21]~73
--operation mode is normal

B1L37Q = B1_PAREG[21];


--B1_PAREG[22] is PhaseAcc:inst|PAREG[22]
--operation mode is normal

B1_PAREG[22]_lut_out = M11_cs_buffer[16];
B1_PAREG[22] = DFFEA(B1_PAREG[22]_lut_out, !B1_FP2, RST, , , , );

--B1L39Q is PhaseAcc:inst|PAREG[22]~74
--operation mode is normal

B1L39Q = B1_PAREG[22];


--B1_PAREG[23] is PhaseAcc:inst|PAREG[23]
--operation mode is normal

B1_PAREG[23]_lut_out = K4_unreg_res_node[17];
B1_PAREG[23] = DFFEA(B1_PAREG[23]_lut_out, !B1_FP2, RST, , , , );

--B1L41Q is PhaseAcc:inst|PAREG[23]~75
--operation mode is normal

B1L41Q = B1_PAREG[23];


--M5L17 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~139
--operation mode is normal

M5L17 = M2L17 $ G1_sanjiaoreg[4] $ M5L14;

--M5L19 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~179
--operation mode is normal

M5L19 = M2L17 $ G1_sanjiaoreg[4] $ M5L14;


--M5L18 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~143
--operation mode is normal

M5L18 = M2L17 & (G1_sanjiaoreg[4] # M5L14) # !M2L17 & G1_sanjiaoreg[4] & M5L14;

--M5L20 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~180
--operation mode is normal

M5L20 = M2L17 & (G1_sanjiaoreg[4] # M5L14) # !M2L17 & G1_sanjiaoreg[4] & M5L14;


--M5L13 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~147
--operation mode is normal

M5L13 = M2L13 $ G1_sanjiaoreg[3] $ M5L10;

--M5L15 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~181
--operation mode is normal

M5L15 = M2L13 $ G1_sanjiaoreg[3] $ M5L10;


--M5L14 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~151
--operation mode is normal

M5L14 = M2L13 & (G1_sanjiaoreg[3] # M5L10) # !M2L13 & G1_sanjiaoreg[3] & M5L10;

--M5L16 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~182
--operation mode is normal

M5L16 = M2L13 & (G1_sanjiaoreg[3] # M5L10) # !M2L13 & G1_sanjiaoreg[3] & M5L10;


--M5L9 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~155
--operation mode is normal

M5L9 = M2L9 $ G1_sanjiaoreg[2] $ M5L6;

--M5L11 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~183
--operation mode is normal

M5L11 = M2L9 $ G1_sanjiaoreg[2] $ M5L6;


--M5L10 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~159
--operation mode is normal

M5L10 = M2L9 & (G1_sanjiaoreg[2] # M5L6) # !M2L9 & G1_sanjiaoreg[2] & M5L6;

--M5L12 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~184
--operation mode is normal

M5L12 = M2L9 & (G1_sanjiaoreg[2] # M5L6) # !M2L9 & G1_sanjiaoreg[2] & M5L6;


--M5L5 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~163
--operation mode is normal

M5L5 = M2L5 $ G1_sanjiaoreg[1] $ M5L2;

--M5L7 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~185
--operation mode is normal

M5L7 = M2L5 $ G1_sanjiaoreg[1] $ M5L2;


--M5L6 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~167
--operation mode is normal

M5L6 = M2L5 & (G1_sanjiaoreg[1] # M5L2) # !M2L5 & G1_sanjiaoreg[1] & M5L2;

--M5L8 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~186
--operation mode is normal

M5L8 = M2L5 & (G1_sanjiaoreg[1] # M5L2) # !M2L5 & G1_sanjiaoreg[1] & M5L2;


--M5L1 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~170
--operation mode is normal

M5L1 = M2L1 $ G1_sanjiaoreg[0];

--M5L3 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~187
--operation mode is normal

M5L3 = M2L1 $ G1_sanjiaoreg[0];


--M5L2 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~173
--operation mode is normal

M5L2 = M2L1 & G1_sanjiaoreg[0];

--M5L4 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~188
--operation mode is normal

M5L4 = M2L1 & G1_sanjiaoreg[0];


--P3_q[5] is lpm_rom_sanjiao:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[5]
P3_q[5]_clock_0 = B1_FP2;
P3_q[5]_clock_1 = B1_FP2;
P3_q[5]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P3_q[5]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P3_q[5] = MEMORY_SEGMENT(, , P3_q[5]_clock_0, P3_q[5]_clock_1, , , , , P3_q[5]_write_address, P3_q[5]_read_address);


--G1_sanjiaoreg[5] is PathSel:inst5|sanjiaoreg[5]
--operation mode is normal

G1_sanjiaoreg[5] = P3_q[5] & PathSel[2];

--G1L39 is PathSel:inst5|sanjiaoreg[5]~58
--operation mode is normal

G1L39 = P3_q[5] & PathSel[2];


--M11_cs_buffer[12] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[12]
--operation mode is arithmetic

M11_cs_buffer[12] = B1_PASTEP[18] $ B1_PAREG[18] $ !M11_cout[11];

--M11L45 is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[12]~336
--operation mode is arithmetic

M11L45 = B1_PASTEP[18] $ B1_PAREG[18] $ !M11_cout[11];

--M11_cout[12] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[12]
--operation mode is arithmetic

M11_cout[12] = CARRY(B1_PASTEP[18] & B1_PAREG[18] & M11_cout[11] # !B1_PASTEP[18] & (B1_PAREG[18] # M11_cout[11]));


--M11_cs_buffer[13] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[13]
--operation mode is arithmetic

M11_cs_buffer[13] = B1_PASTEP[19] $ B1_PAREG[19] $ M11_cout[12];

--M11L47 is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[13]~337
--operation mode is arithmetic

M11L47 = B1_PASTEP[19] $ B1_PAREG[19] $ M11_cout[12];

--M11_cout[13] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[13]
--operation mode is arithmetic

M11_cout[13] = CARRY(B1_PASTEP[19] & (B1_PAREG[19] # M11_cout[12]) # !B1_PASTEP[19] & B1_PAREG[19] & M11_cout[12]);


--M11_cs_buffer[14] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[14]
--operation mode is arithmetic

M11_cs_buffer[14] = B1_PASTEP[20] $ B1_PAREG[20] $ M11_cout[13];

--M11L49 is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[14]~338
--operation mode is arithmetic

M11L49 = B1_PASTEP[20] $ B1_PAREG[20] $ M11_cout[13];

--M11_cout[14] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[14]
--operation mode is arithmetic

M11_cout[14] = CARRY(B1_PASTEP[20] & (B1_PAREG[20] # M11_cout[13]) # !B1_PASTEP[20] & B1_PAREG[20] & M11_cout[13]);


--M11_cs_buffer[15] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[15]
--operation mode is arithmetic

M11_cs_buffer[15] = B1_PASTEP[21] $ B1_PAREG[21] $ M11_cout[14];

--M11L51 is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[15]~339
--operation mode is arithmetic

M11L51 = B1_PASTEP[21] $ B1_PAREG[21] $ M11_cout[14];

--M11_cout[15] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[15]
--operation mode is arithmetic

M11_cout[15] = CARRY(B1_PASTEP[21] & (B1_PAREG[21] # M11_cout[14]) # !B1_PASTEP[21] & B1_PAREG[21] & M11_cout[14]);


--M11_cs_buffer[16] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[16]
--operation mode is arithmetic

M11_cs_buffer[16] = B1_PASTEP[22] $ B1_PAREG[22] $ M11_cout[15];

--M11L53 is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[16]~340
--operation mode is arithmetic

M11L53 = B1_PASTEP[22] $ B1_PAREG[22] $ M11_cout[15];

--M11_cout[16] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[16]
--operation mode is arithmetic

M11_cout[16] = CARRY(B1_PASTEP[22] & (B1_PAREG[22] # M11_cout[15]) # !B1_PASTEP[22] & B1_PAREG[22] & M11_cout[15]);


--P3_q[4] is lpm_rom_sanjiao:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[4]
P3_q[4]_clock_0 = B1_FP2;
P3_q[4]_clock_1 = B1_FP2;
P3_q[4]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P3_q[4]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P3_q[4] = MEMORY_SEGMENT(, , P3_q[4]_clock_0, P3_q[4]_clock_1, , , , , P3_q[4]_write_address, P3_q[4]_read_address);


--G1_sanjiaoreg[4] is PathSel:inst5|sanjiaoreg[4]
--operation mode is normal

G1_sanjiaoreg[4] = PathSel[2] & P3_q[4];

--G1L37 is PathSel:inst5|sanjiaoreg[4]~59
--operation mode is normal

G1L37 = PathSel[2] & P3_q[4];


--P3_q[3] is lpm_rom_sanjiao:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[3]
P3_q[3]_clock_0 = B1_FP2;
P3_q[3]_clock_1 = B1_FP2;
P3_q[3]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P3_q[3]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P3_q[3] = MEMORY_SEGMENT(, , P3_q[3]_clock_0, P3_q[3]_clock_1, , , , , P3_q[3]_write_address, P3_q[3]_read_address);


--G1_sanjiaoreg[3] is PathSel:inst5|sanjiaoreg[3]
--operation mode is normal

G1_sanjiaoreg[3] = PathSel[2] & P3_q[3];

--G1L35 is PathSel:inst5|sanjiaoreg[3]~60
--operation mode is normal

G1L35 = PathSel[2] & P3_q[3];


--P3_q[2] is lpm_rom_sanjiao:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[2]
P3_q[2]_clock_0 = B1_FP2;
P3_q[2]_clock_1 = B1_FP2;
P3_q[2]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P3_q[2]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P3_q[2] = MEMORY_SEGMENT(, , P3_q[2]_clock_0, P3_q[2]_clock_1, , , , , P3_q[2]_write_address, P3_q[2]_read_address);


--G1_sanjiaoreg[2] is PathSel:inst5|sanjiaoreg[2]
--operation mode is normal

G1_sanjiaoreg[2] = PathSel[2] & P3_q[2];

--G1L33 is PathSel:inst5|sanjiaoreg[2]~61
--operation mode is normal

G1L33 = PathSel[2] & P3_q[2];


--P3_q[1] is lpm_rom_sanjiao:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[1]
P3_q[1]_clock_0 = B1_FP2;
P3_q[1]_clock_1 = B1_FP2;
P3_q[1]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P3_q[1]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P3_q[1] = MEMORY_SEGMENT(, , P3_q[1]_clock_0, P3_q[1]_clock_1, , , , , P3_q[1]_write_address, P3_q[1]_read_address);


--G1_sanjiaoreg[1] is PathSel:inst5|sanjiaoreg[1]
--operation mode is normal

G1_sanjiaoreg[1] = PathSel[2] & P3_q[1];

--G1L31 is PathSel:inst5|sanjiaoreg[1]~62
--operation mode is normal

G1L31 = PathSel[2] & P3_q[1];


--P3_q[0] is lpm_rom_sanjiao:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[0]
P3_q[0]_clock_0 = B1_FP2;
P3_q[0]_clock_1 = B1_FP2;
P3_q[0]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P3_q[0]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P3_q[0] = MEMORY_SEGMENT(, , P3_q[0]_clock_0, P3_q[0]_clock_1, , , , , P3_q[0]_write_address, P3_q[0]_read_address);


--G1_sanjiaoreg[0] is PathSel:inst5|sanjiaoreg[0]
--operation mode is normal

G1_sanjiaoreg[0] = PathSel[2] & P3_q[0];

--G1L29 is PathSel:inst5|sanjiaoreg[0]~63
--operation mode is normal

G1L29 = PathSel[2] & P3_q[0];


--M2L21 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~103
--operation mode is normal

M2L21 = G1_sinreg[5] $ G1_juchireg[5] $ M2L18;

--M2L23 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~147
--operation mode is normal

M2L23 = G1_sinreg[5] $ G1_juchireg[5] $ M2L18;


--M2L22 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~107
--operation mode is normal

M2L22 = G1_sinreg[5] & (G1_juchireg[5] # M2L18) # !G1_sinreg[5] & G1_juchireg[5] & M2L18;

--M2L24 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~148
--operation mode is normal

M2L24 = G1_sinreg[5] & (G1_juchireg[5] # M2L18) # !G1_sinreg[5] & G1_juchireg[5] & M2L18;


--B1_PASTEP[23] is PhaseAcc:inst|PASTEP[23]
--operation mode is normal

B1_PASTEP[23]_lut_out = FreDec & K5_unreg_res_node[17] # !FreDec & (!K6_unreg_res_node[17]);
B1_PASTEP[23] = DFFEA(B1_PASTEP[23]_lut_out, B1_EVENTCHECK, RST, , , , );

--B1L80Q is PhaseAcc:inst|PASTEP[23]~372
--operation mode is normal