dds.map.eqn

利用FPGA的资源实现任意波形的产生

-- Copyright (C) 1991-2005 Altera Corporation
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--K3_unreg_res_node[8] is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|unreg_res_node[8]
--operation mode is normal

K3_unreg_res_node[8] = M8L26 $ M5L26;

--K3L3 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|unreg_res_node[8]~22
--operation mode is normal

K3L3 = M8L26 $ M5L26;


--M8L25 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~83
--operation mode is normal

M8L25 = M5L25 $ (M8L22);

--M8L27 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~133
--operation mode is normal

M8L27 = M5L25 $ (M8L22);


--M8L26 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~86
--operation mode is normal

M8L26 = M5L25 & (M8L22);

--M8L28 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~134
--operation mode is normal

M8L28 = M5L25 & (M8L22);


--M8L21 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~90
--operation mode is normal

M8L21 = M5L21 $ G1_fangboreg[5] $ M8L18;

--M8L23 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~135
--operation mode is normal

M8L23 = M5L21 $ G1_fangboreg[5] $ M8L18;


--M8L22 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~94
--operation mode is normal

M8L22 = M5L21 & (G1_fangboreg[5] # M8L18) # !M5L21 & G1_fangboreg[5] & M8L18;

--M8L24 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~136
--operation mode is normal

M8L24 = M5L21 & (G1_fangboreg[5] # M8L18) # !M5L21 & G1_fangboreg[5] & M8L18;


--M8L17 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~98
--operation mode is normal

M8L17 = M5L17 $ G1_fangboreg[4] $ M8L14;

--M8L19 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~137
--operation mode is normal

M8L19 = M5L17 $ G1_fangboreg[4] $ M8L14;


--M8L18 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~102
--operation mode is normal

M8L18 = M5L17 & (G1_fangboreg[4] # M8L14) # !M5L17 & G1_fangboreg[4] & M8L14;

--M8L20 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~138
--operation mode is normal

M8L20 = M5L17 & (G1_fangboreg[4] # M8L14) # !M5L17 & G1_fangboreg[4] & M8L14;


--M8L13 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~106
--operation mode is normal

M8L13 = M5L13 $ G1_fangboreg[3] $ M8L10;

--M8L15 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~139
--operation mode is normal

M8L15 = M5L13 $ G1_fangboreg[3] $ M8L10;


--M8L14 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~110
--operation mode is normal

M8L14 = M5L13 & (G1_fangboreg[3] # M8L10) # !M5L13 & G1_fangboreg[3] & M8L10;

--M8L16 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~140
--operation mode is normal

M8L16 = M5L13 & (G1_fangboreg[3] # M8L10) # !M5L13 & G1_fangboreg[3] & M8L10;


--M8L9 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~114
--operation mode is normal

M8L9 = M5L9 $ G1_fangboreg[2] $ M8L6;

--M8L11 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~141
--operation mode is normal

M8L11 = M5L9 $ G1_fangboreg[2] $ M8L6;


--M8L10 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~118
--operation mode is normal

M8L10 = M5L9 & (G1_fangboreg[2] # M8L6) # !M5L9 & G1_fangboreg[2] & M8L6;

--M8L12 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~142
--operation mode is normal

M8L12 = M5L9 & (G1_fangboreg[2] # M8L6) # !M5L9 & G1_fangboreg[2] & M8L6;


--M8L5 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~122
--operation mode is normal

M8L5 = M5L5 $ G1_fangboreg[1] $ M8L2;

--M8L7 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~143
--operation mode is normal

M8L7 = M5L5 $ G1_fangboreg[1] $ M8L2;


--M8L6 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~126
--operation mode is normal

M8L6 = M5L5 & (G1_fangboreg[1] # M8L2) # !M5L5 & G1_fangboreg[1] & M8L2;

--M8L8 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~144
--operation mode is normal

M8L8 = M5L5 & (G1_fangboreg[1] # M8L2) # !M5L5 & G1_fangboreg[1] & M8L2;


--M8L1 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~129
--operation mode is normal

M8L1 = M5L1 $ G1_fangboreg[0];

--M8L3 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~145
--operation mode is normal

M8L3 = M5L1 $ G1_fangboreg[0];


--M8L2 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~132
--operation mode is normal

M8L2 = M5L1 # G1_fangboreg[0];

--M8L4 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~146
--operation mode is normal

M8L4 = M5L1 # G1_fangboreg[0];


--P1_q[5] is lpm_rom_fangbo:inst4|lpm_rom:lpm_rom_component|altrom:srom|q[5]
P1_q[5]_clock_0 = B1_FP2;
P1_q[5]_clock_1 = B1_FP2;
P1_q[5]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P1_q[5]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P1_q[5] = MEMORY_SEGMENT(, , P1_q[5]_clock_0, P1_q[5]_clock_1, , , , , P1_q[5]_write_address, P1_q[5]_read_address);


--G1_fangboreg[5] is PathSel:inst5|fangboreg[5]
--operation mode is normal

G1_fangboreg[5] = P1_q[5] & PathSel[3];

--G1L13 is PathSel:inst5|fangboreg[5]~65
--operation mode is normal

G1L13 = P1_q[5] & PathSel[3];


--P1_q[4] is lpm_rom_fangbo:inst4|lpm_rom:lpm_rom_component|altrom:srom|q[4]
P1_q[4]_clock_0 = B1_FP2;
P1_q[4]_clock_1 = B1_FP2;
P1_q[4]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P1_q[4]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P1_q[4] = MEMORY_SEGMENT(, , P1_q[4]_clock_0, P1_q[4]_clock_1, , , , , P1_q[4]_write_address, P1_q[4]_read_address);


--G1_fangboreg[4] is PathSel:inst5|fangboreg[4]
--operation mode is normal

G1_fangboreg[4] = PathSel[3] & P1_q[4];

--G1L11 is PathSel:inst5|fangboreg[4]~66
--operation mode is normal

G1L11 = PathSel[3] & P1_q[4];


--P1_q[3] is lpm_rom_fangbo:inst4|lpm_rom:lpm_rom_component|altrom:srom|q[3]
P1_q[3]_clock_0 = B1_FP2;
P1_q[3]_clock_1 = B1_FP2;
P1_q[3]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P1_q[3]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P1_q[3] = MEMORY_SEGMENT(, , P1_q[3]_clock_0, P1_q[3]_clock_1, , , , , P1_q[3]_write_address, P1_q[3]_read_address);


--G1_fangboreg[3] is PathSel:inst5|fangboreg[3]
--operation mode is normal

G1_fangboreg[3] = PathSel[3] & P1_q[3];

--G1L9 is PathSel:inst5|fangboreg[3]~67
--operation mode is normal

G1L9 = PathSel[3] & P1_q[3];


--P1_q[2] is lpm_rom_fangbo:inst4|lpm_rom:lpm_rom_component|altrom:srom|q[2]
P1_q[2]_clock_0 = B1_FP2;
P1_q[2]_clock_1 = B1_FP2;
P1_q[2]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P1_q[2]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P1_q[2] = MEMORY_SEGMENT(, , P1_q[2]_clock_0, P1_q[2]_clock_1, , , , , P1_q[2]_write_address, P1_q[2]_read_address);


--G1_fangboreg[2] is PathSel:inst5|fangboreg[2]
--operation mode is normal

G1_fangboreg[2] = PathSel[3] & P1_q[2];

--G1L7 is PathSel:inst5|fangboreg[2]~68
--operation mode is normal

G1L7 = PathSel[3] & P1_q[2];


--P1_q[1] is lpm_rom_fangbo:inst4|lpm_rom:lpm_rom_component|altrom:srom|q[1]
P1_q[1]_clock_0 = B1_FP2;
P1_q[1]_clock_1 = B1_FP2;
P1_q[1]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P1_q[1]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P1_q[1] = MEMORY_SEGMENT(, , P1_q[1]_clock_0, P1_q[1]_clock_1, , , , , P1_q[1]_write_address, P1_q[1]_read_address);


--G1_fangboreg[1] is PathSel:inst5|fangboreg[1]
--operation mode is normal

G1_fangboreg[1] = PathSel[3] & P1_q[1];

--G1L5 is PathSel:inst5|fangboreg[1]~69
--operation mode is normal

G1L5 = PathSel[3] & P1_q[1];


--P1_q[0] is lpm_rom_fangbo:inst4|lpm_rom:lpm_rom_component|altrom:srom|q[0]
P1_q[0]_clock_0 = B1_FP2;
P1_q[0]_clock_1 = B1_FP2;
P1_q[0]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P1_q[0]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23]);
P1_q[0] = MEMORY_SEGMENT(, , P1_q[0]_clock_0, P1_q[0]_clock_1, , , , , P1_q[0]_write_address, P1_q[0]_read_address);


--G1_fangboreg[0] is PathSel:inst5|fangboreg[0]
--operation mode is normal

G1_fangboreg[0] = PathSel[3] & P1_q[0];

--G1L3 is PathSel:inst5|fangboreg[0]~70
--operation mode is normal

G1L3 = PathSel[3] & P1_q[0];


--M5L25 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~124
--operation mode is normal

M5L25 = M2L22 $ (M5L22);

--M5L27 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~175
--operation mode is normal

M5L27 = M2L22 $ (M5L22);


--M5L26 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~127
--operation mode is normal

M5L26 = M2L22 & (M5L22);

--M5L28 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~176
--operation mode is normal

M5L28 = M2L22 & (M5L22);


--M5L21 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~131
--operation mode is normal

M5L21 = M2L21 $ G1_sanjiaoreg[5] $ M5L18;

--M5L23 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~177
--operation mode is normal

M5L23 = M2L21 $ G1_sanjiaoreg[5] $ M5L18;


--M5L22 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~135
--operation mode is normal

M5L22 = M2L21 & (G1_sanjiaoreg[5] # M5L18) # !M2L21 & G1_sanjiaoreg[5] & M5L18;

--M5L24 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~178
--operation mode is normal

M5L24 = M2L21 & (G1_sanjiaoreg[5] # M5L18) # !M2L21 & G1_sanjiaoreg[5] & M5L18;


--B1_FP2 is PhaseAcc:inst|FP2
--operation mode is normal

B1_FP2_lut_out = !B1_FP2;
B1_FP2 = DFFEA(B1_FP2_lut_out, !CLK, RST, , , , );

--B1L4Q is PhaseAcc:inst|FP2~1
--operation mode is normal

B1L4Q = B1_FP2;


--B1_PAREG[18] is PhaseAcc:inst|PAREG[18]
--operation mode is normal

B1_PAREG[18]_lut_out = M11_cs_buffer[12];
B1_PAREG[18] = DFFEA(B1_PAREG[18]_lut_out, !B1_FP2, RST, , , , );

--B1L31Q is PhaseAcc:inst|PAREG[18]~70
--operation mode is normal

B1L31Q = B1_PAREG[18];


--B1_PAREG[19] is PhaseAcc:inst|PAREG[19]
--operation mode is normal

B1_PAREG[19]_lut_out = M11_cs_buffer[13];
B1_PAREG[19] = DFFEA(B1_PAREG[19]_lut_out, !B1_FP2, RST, , , , );

--B1L33Q is PhaseAcc:inst|PAREG[19]~71
--operation mode is normal

B1L33Q = B1_PAREG[19];


--B1_PAREG[20] is PhaseAcc:inst|PAREG[20]
--operation mode is normal

B1_PAREG[20]_lut_out = M11_cs_buffer[14];
B1_PAREG[20] = DFFEA(B1_PAREG[20]_lut_out, !B1_FP2, RST, , , , );