pathsel.vhd

利用FPGA的资源实现任意波形的产生

-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.


-- Generated by Quartus II Version 5.1 (Build Build 176 10/26/2005)
-- Created on Wed Sep 13 23:25:23 2006

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
--  Entity Declaration

ENTITY PathSel IS
	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	PORT
	(
		sin : IN STD_LOGIC_VECTOR(5 downto 0);
		juchi : IN STD_LOGIC_VECTOR(5 downto 0);
		sanjiao : IN STD_LOGIC_VECTOR(5 downto 0);
		fangbo : IN STD_LOGIC_VECTOR(5 downto 0);
		PathSel : IN STD_LOGIC_VECTOR(3 downto 0);
		AddOut : OUT STD_LOGIC_VECTOR(7 downto 0)
	);
	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	
END PathSel;


--  Architecture Body

ARCHITECTURE PathSel_architecture OF PathSel IS
signal				sinreg				:STD_LOGIC_VECTOR(5 downto 0);
signal				juchireg			:STD_LOGIC_VECTOR(5 downto 0);
signal				sanjiaoreg			:STD_LOGIC_VECTOR(5 downto 0);
signal				fangboreg			:STD_LOGIC_VECTOR(5 downto 0);
signal				WaveAdd				:INTEGER RANGE 0 TO 255;	
BEGIN	
	sinreg(5 downto 0)<=(sin(5)AND PathSel(0))&(sin(4)AND PathSel(0))&(sin(3)AND PathSel(0))&(sin(2)AND PathSel(0))&(sin(1)AND PathSel(0))&(sin(0)AND PathSel(0));
	juchireg(5 downto 0)<=(juchi(5)AND PathSel(1))&(juchi(4)AND PathSel(1))&(juchi(3)AND PathSel(1))&(juchi(2)AND PathSel(1))&(juchi(1)AND PathSel(1))&(juchi(0)AND PathSel(1));
	sanjiaoreg(5 downto 0)<=(sanjiao(5)AND PathSel(2))&(sanjiao(4)AND PathSel(2))&(sanjiao(3)AND PathSel(2))&(sanjiao(2)AND PathSel(2))&(sanjiao(1)AND PathSel(2))&(sanjiao(0)AND PathSel(2));
	fangboreg(5 downto 0)<=(fangbo(5)AND PathSel(3))&(fangbo(4)AND PathSel(3))&(fangbo(3)AND PathSel(3))&(fangbo(2)AND PathSel(3))&(fangbo(1)AND PathSel(3))&(fangbo(0)AND PathSel(3));
	WaveAdd<=CONV_INTEGER(sinreg(5 downto 0))+CONV_INTEGER(juchireg(5 downto 0))+CONV_INTEGER(sanjiaoreg(5 downto 0))+CONV_INTEGER(fangboreg(5 downto 0));
	AddOut(7 downto 0)<=CONV_STD_LOGIC_VECTOR(WaveAdd,8);	
END PathSel_architecture;