dds.fit.summary

利用FPGA的资源实现任意波形的产生

Fitter Status : Successful - Thu Oct 05 13:49:57 2006
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : DDS
Top-level Entity Name : DDS
Family : ACEX1K
Device : EP1K50TC144-1
Timing Models : Final
Total logic elements : 158 / 2,880 ( 5 % )
Total pins : 16 / 102 ( 16 % )
Total memory bits : 1,536 / 40,960 ( 4 % )
Total PLLs : 0 / 1 ( 0 % )