dds.hier_info

利用FPGA的资源实现任意波形的产生

|DDS
toda[0] <= SUB:inst6.toda[0]
toda[1] <= SUB:inst6.toda[1]
toda[2] <= SUB:inst6.toda[2]
toda[3] <= SUB:inst6.toda[3]
toda[4] <= SUB:inst6.toda[4]
toda[5] <= SUB:inst6.toda[5]
toda[6] <= SUB:inst6.toda[6]
toda[7] <= SUB:inst6.toda[7]
CLK => PhaseAcc:inst.CLK
RST => PhaseAcc:inst.RST
FreDec => PhaseAcc:inst.FreDec
FreInc => PhaseAcc:inst.FreInc
PathSel[0] => PathSel:inst5.PathSel[0]
PathSel[1] => PathSel:inst5.PathSel[1]
PathSel[2] => PathSel:inst5.PathSel[2]
PathSel[3] => PathSel:inst5.PathSel[3]


|DDS|SUB:inst6
AddOut[0] => add~0.IN16
AddOut[1] => add~0.IN15
AddOut[2] => add~0.IN14
AddOut[3] => add~0.IN13
AddOut[4] => add~0.IN12
AddOut[5] => add~0.IN11
AddOut[6] => add~0.IN10
AddOut[7] => add~0.IN9
toda[0] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
toda[1] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
toda[2] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
toda[3] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
toda[4] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
toda[5] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
toda[6] <= add~0.DB_MAX_OUTPUT_PORT_TYPE
toda[7] <= add~0.DB_MAX_OUTPUT_PORT_TYPE


|DDS|PathSel:inst5
sin[0] => sinreg[0].IN1
sin[1] => sinreg[1].IN1
sin[2] => sinreg[2].IN1
sin[3] => sinreg[3].IN1
sin[4] => sinreg[4].IN1
sin[5] => sinreg[5].IN0
juchi[0] => juchireg[0].IN1
juchi[1] => juchireg[1].IN1
juchi[2] => juchireg[2].IN1
juchi[3] => juchireg[3].IN1
juchi[4] => juchireg[4].IN1
juchi[5] => juchireg[5].IN0
sanjiao[0] => sanjiaoreg[0].IN1
sanjiao[1] => sanjiaoreg[1].IN1
sanjiao[2] => sanjiaoreg[2].IN1
sanjiao[3] => sanjiaoreg[3].IN1
sanjiao[4] => sanjiaoreg[4].IN1
sanjiao[5] => sanjiaoreg[5].IN0
fangbo[0] => fangboreg[0].IN1
fangbo[1] => fangboreg[1].IN1
fangbo[2] => fangboreg[2].IN1
fangbo[3] => fangboreg[3].IN1
fangbo[4] => fangboreg[4].IN1
fangbo[5] => fangboreg[5].IN0
PathSel[0] => sinreg[5].IN1
PathSel[0] => sinreg[4].IN0
PathSel[0] => sinreg[3].IN0
PathSel[0] => sinreg[2].IN0
PathSel[0] => sinreg[1].IN0
PathSel[0] => sinreg[0].IN0
PathSel[1] => juchireg[5].IN1
PathSel[1] => juchireg[4].IN0
PathSel[1] => juchireg[3].IN0
PathSel[1] => juchireg[2].IN0
PathSel[1] => juchireg[1].IN0
PathSel[1] => juchireg[0].IN0
PathSel[2] => sanjiaoreg[5].IN1
PathSel[2] => sanjiaoreg[4].IN0
PathSel[2] => sanjiaoreg[3].IN0
PathSel[2] => sanjiaoreg[2].IN0
PathSel[2] => sanjiaoreg[1].IN0
PathSel[2] => sanjiaoreg[0].IN0
PathSel[3] => fangboreg[5].IN1
PathSel[3] => fangboreg[4].IN0
PathSel[3] => fangboreg[3].IN0
PathSel[3] => fangboreg[2].IN0
PathSel[3] => fangboreg[1].IN0
PathSel[3] => fangboreg[0].IN0
AddOut[0] <= add~2.DB_MAX_OUTPUT_PORT_TYPE
AddOut[1] <= add~2.DB_MAX_OUTPUT_PORT_TYPE
AddOut[2] <= add~2.DB_MAX_OUTPUT_PORT_TYPE
AddOut[3] <= add~2.DB_MAX_OUTPUT_PORT_TYPE
AddOut[4] <= add~2.DB_MAX_OUTPUT_PORT_TYPE
AddOut[5] <= add~2.DB_MAX_OUTPUT_PORT_TYPE
AddOut[6] <= add~2.DB_MAX_OUTPUT_PORT_TYPE
AddOut[7] <= add~2.DB_MAX_OUTPUT_PORT_TYPE


|DDS|lpm_rom_fangbo:inst4
address[0] => lpm_rom:lpm_rom_component.address[0]
address[1] => lpm_rom:lpm_rom_component.address[1]
address[2] => lpm_rom:lpm_rom_component.address[2]
address[3] => lpm_rom:lpm_rom_component.address[3]
address[4] => lpm_rom:lpm_rom_component.address[4]
address[5] => lpm_rom:lpm_rom_component.address[5]
inclock => lpm_rom:lpm_rom_component.inclock
outclock => lpm_rom:lpm_rom_component.outclock
q[0] <= lpm_rom:lpm_rom_component.q[0]
q[1] <= lpm_rom:lpm_rom_component.q[1]
q[2] <= lpm_rom:lpm_rom_component.q[2]
q[3] <= lpm_rom:lpm_rom_component.q[3]
q[4] <= lpm_rom:lpm_rom_component.q[4]
q[5] <= lpm_rom:lpm_rom_component.q[5]


|DDS|lpm_rom_fangbo:inst4|lpm_rom:lpm_rom_component
address[0] => altrom:srom.address[0]
address[1] => altrom:srom.address[1]
address[2] => altrom:srom.address[2]
address[3] => altrom:srom.address[3]
address[4] => altrom:srom.address[4]
address[5] => altrom:srom.address[5]
inclock => altrom:srom.clocki
outclock => altrom:srom.clocko
memenab => otri[5].OE
memenab => otri[4].OE
memenab => otri[3].OE
memenab => otri[2].OE
memenab => otri[1].OE
memenab => otri[0].OE
q[0] <= otri[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= otri[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= otri[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= otri[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= otri[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= otri[5].DB_MAX_OUTPUT_PORT_TYPE


|DDS|lpm_rom_fangbo:inst4|lpm_rom:lpm_rom_component|altrom:srom
address[0] => segment[0][5].WADDR
address[0] => segment[0][5].RADDR
address[0] => segment[0][4].WADDR
address[0] => segment[0][4].RADDR
address[0] => segment[0][3].WADDR
address[0] => segment[0][3].RADDR
address[0] => segment[0][2].WADDR
address[0] => segment[0][2].RADDR
address[0] => segment[0][1].WADDR
address[0] => segment[0][1].RADDR
address[0] => segment[0][0].WADDR
address[0] => segment[0][0].RADDR
address[1] => segment[0][5].WADDR1
address[1] => segment[0][5].RADDR1
address[1] => segment[0][4].WADDR1
address[1] => segment[0][4].RADDR1
address[1] => segment[0][3].WADDR1
address[1] => segment[0][3].RADDR1
address[1] => segment[0][2].WADDR1
address[1] => segment[0][2].RADDR1
address[1] => segment[0][1].WADDR1
address[1] => segment[0][1].RADDR1
address[1] => segment[0][0].WADDR1
address[1] => segment[0][0].RADDR1
address[2] => segment[0][5].WADDR2
address[2] => segment[0][5].RADDR2
address[2] => segment[0][4].WADDR2
address[2] => segment[0][4].RADDR2
address[2] => segment[0][3].WADDR2
address[2] => segment[0][3].RADDR2
address[2] => segment[0][2].WADDR2
address[2] => segment[0][2].RADDR2
address[2] => segment[0][1].WADDR2
address[2] => segment[0][1].RADDR2
address[2] => segment[0][0].WADDR2
address[2] => segment[0][0].RADDR2
address[3] => segment[0][5].WADDR3
address[3] => segment[0][5].RADDR3
address[3] => segment[0][4].WADDR3
address[3] => segment[0][4].RADDR3
address[3] => segment[0][3].WADDR3
address[3] => segment[0][3].RADDR3
address[3] => segment[0][2].WADDR3
address[3] => segment[0][2].RADDR3
address[3] => segment[0][1].WADDR3
address[3] => segment[0][1].RADDR3
address[3] => segment[0][0].WADDR3
address[3] => segment[0][0].RADDR3
address[4] => segment[0][5].WADDR4
address[4] => segment[0][5].RADDR4
address[4] => segment[0][4].WADDR4
address[4] => segment[0][4].RADDR4
address[4] => segment[0][3].WADDR4
address[4] => segment[0][3].RADDR4
address[4] => segment[0][2].WADDR4
address[4] => segment[0][2].RADDR4
address[4] => segment[0][1].WADDR4
address[4] => segment[0][1].RADDR4
address[4] => segment[0][0].WADDR4
address[4] => segment[0][0].RADDR4
address[5] => segment[0][5].WADDR5
address[5] => segment[0][5].RADDR5
address[5] => segment[0][4].WADDR5
address[5] => segment[0][4].RADDR5
address[5] => segment[0][3].WADDR5
address[5] => segment[0][3].RADDR5
address[5] => segment[0][2].WADDR5
address[5] => segment[0][2].RADDR5
address[5] => segment[0][1].WADDR5
address[5] => segment[0][1].RADDR5
address[5] => segment[0][0].WADDR5
address[5] => segment[0][0].RADDR5
clocki => segment[0][5].CLK0
clocki => segment[0][4].CLK0
clocki => segment[0][3].CLK0
clocki => segment[0][2].CLK0
clocki => segment[0][1].CLK0
clocki => segment[0][0].CLK0
clocko => segment[0][5].CLK1
clocko => segment[0][4].CLK1
clocko => segment[0][3].CLK1
clocko => segment[0][2].CLK1
clocko => segment[0][1].CLK1
clocko => segment[0][0].CLK1
q[0] <= segment[0][0].DATAOUT
q[1] <= segment[0][1].DATAOUT
q[2] <= segment[0][2].DATAOUT
q[3] <= segment[0][3].DATAOUT
q[4] <= segment[0][4].DATAOUT
q[5] <= segment[0][5].DATAOUT


|DDS|PhaseAcc:inst
CLK => FP2.CLK
RST => PAREG[22].ACLR
RST => PAREG[21].ACLR
RST => PAREG[20].ACLR
RST => PAREG[19].ACLR
RST => PAREG[18].ACLR
RST => PAREG[17].ACLR
RST => PAREG[16].ACLR
RST => PAREG[15].ACLR
RST => PAREG[14].ACLR
RST => PAREG[13].ACLR
RST => PAREG[12].ACLR
RST => PAREG[11].ACLR
RST => PAREG[10].ACLR
RST => PAREG[9].ACLR
RST => PAREG[8].ACLR
RST => PAREG[7].ACLR
RST => PAREG[6].ACLR
RST => PAREG[5].ACLR
RST => PAREG[4].ACLR
RST => PAREG[3].ACLR
RST => PAREG[2].ACLR
RST => PAREG[1].ACLR
RST => PAREG[0].ACLR
RST => FP2.ACLR
RST => PAREG[23].ACLR
RST => PASTEP[22].ACLR
RST => PASTEP[21].ACLR
RST => PASTEP[20].ACLR
RST => PASTEP[19].ACLR
RST => PASTEP[18].PRESET
RST => PASTEP[17].ACLR
RST => PASTEP[16].ACLR
RST => PASTEP[15].ACLR
RST => PASTEP[14].ACLR
RST => PASTEP[13].ACLR
RST => PASTEP[12].ACLR
RST => PASTEP[11].ACLR
RST => PASTEP[10].ACLR
RST => PASTEP[9].ACLR
RST => PASTEP[8].ACLR
RST => PASTEP[7].ACLR
RST => PASTEP[6].ACLR
RST => PASTEP[23].ACLR
FreDec => EVENTCHECK.IN1
FreDec => PASTEP~18.OUTPUTSELECT
FreDec => PASTEP~19.OUTPUTSELECT
FreDec => PASTEP~20.OUTPUTSELECT
FreDec => PASTEP~21.OUTPUTSELECT
FreDec => PASTEP~22.OUTPUTSELECT
FreDec => PASTEP~23.OUTPUTSELECT
FreDec => PASTEP~24.OUTPUTSELECT
FreDec => PASTEP~25.OUTPUTSELECT
FreDec => PASTEP~26.OUTPUTSELECT
FreDec => PASTEP~27.OUTPUTSELECT
FreDec => PASTEP~28.OUTPUTSELECT
FreDec => PASTEP~29.OUTPUTSELECT
FreDec => PASTEP~30.OUTPUTSELECT
FreDec => PASTEP~31.OUTPUTSELECT
FreDec => PASTEP~32.OUTPUTSELECT
FreDec => PASTEP~33.OUTPUTSELECT
FreDec => PASTEP~34.OUTPUTSELECT
FreDec => PASTEP~35.OUTPUTSELECT
FreInc => EVENTCHECK.IN0
FreInc => PASTEP~0.OUTPUTSELECT
FreInc => PASTEP~1.OUTPUTSELECT
FreInc => PASTEP~2.OUTPUTSELECT
FreInc => PASTEP~3.OUTPUTSELECT
FreInc => PASTEP~4.OUTPUTSELECT
FreInc => PASTEP~5.OUTPUTSELECT
FreInc => PASTEP~6.OUTPUTSELECT
FreInc => PASTEP~7.OUTPUTSELECT
FreInc => PASTEP~8.OUTPUTSELECT
FreInc => PASTEP~9.OUTPUTSELECT
FreInc => PASTEP~10.OUTPUTSELECT
FreInc => PASTEP~11.OUTPUTSELECT
FreInc => PASTEP~12.OUTPUTSELECT
FreInc => PASTEP~13.OUTPUTSELECT
FreInc => PASTEP~14.OUTPUTSELECT
FreInc => PASTEP~15.OUTPUTSELECT
FreInc => PASTEP~16.OUTPUTSELECT
FreInc => PASTEP~17.OUTPUTSELECT
ADCLK <= FP2.DB_MAX_OUTPUT_PORT_TYPE
addr[0] <= PAREG[18].DB_MAX_OUTPUT_PORT_TYPE
addr[1] <= PAREG[19].DB_MAX_OUTPUT_PORT_TYPE
addr[2] <= PAREG[20].DB_MAX_OUTPUT_PORT_TYPE
addr[3] <= PAREG[21].DB_MAX_OUTPUT_PORT_TYPE
addr[4] <= PAREG[22].DB_MAX_OUTPUT_PORT_TYPE
addr[5] <= PAREG[23].DB_MAX_OUTPUT_PORT_TYPE


|DDS|lpm_rom_juchi:inst2
address[0] => lpm_rom:lpm_rom_component.address[0]
address[1] => lpm_rom:lpm_rom_component.address[1]
address[2] => lpm_rom:lpm_rom_component.address[2]
address[3] => lpm_rom:lpm_rom_component.address[3]
address[4] => lpm_rom:lpm_rom_component.address[4]
address[5] => lpm_rom:lpm_rom_component.address[5]
inclock => lpm_rom:lpm_rom_component.inclock
outclock => lpm_rom:lpm_rom_component.outclock
q[0] <= lpm_rom:lpm_rom_component.q[0]
q[1] <= lpm_rom:lpm_rom_component.q[1]
q[2] <= lpm_rom:lpm_rom_component.q[2]
q[3] <= lpm_rom:lpm_rom_component.q[3]
q[4] <= lpm_rom:lpm_rom_component.q[4]
q[5] <= lpm_rom:lpm_rom_component.q[5]


|DDS|lpm_rom_juchi:inst2|lpm_rom:lpm_rom_component
address[0] => altrom:srom.address[0]
address[1] => altrom:srom.address[1]
address[2] => altrom:srom.address[2]
address[3] => altrom:srom.address[3]
address[4] => altrom:srom.address[4]
address[5] => altrom:srom.address[5]
inclock => altrom:srom.clocki
outclock => altrom:srom.clocko
memenab => otri[5].OE
memenab => otri[4].OE
memenab => otri[3].OE
memenab => otri[2].OE
memenab => otri[1].OE
memenab => otri[0].OE
q[0] <= otri[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= otri[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= otri[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= otri[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= otri[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= otri[5].DB_MAX_OUTPUT_PORT_TYPE