dds.map.qmsg

利用FPGA的资源实现任意波形的产生

{ "Warning" "WSGN_SEARCH_FILE" "lpm_rom_juchi.tdf 1 1 " "Warning: Using design file lpm_rom_juchi.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_rom_juchi " "Info: Found entity 1: lpm_rom_juchi" {  } { { "lpm_rom_juchi.tdf" "" { Text "F:/Projects/VHDL/DDS/lpm_rom_juchi.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom_juchi lpm_rom_juchi:inst2 " "Info: Elaborating entity \"lpm_rom_juchi\" for hierarchy \"lpm_rom_juchi:inst2\"" {  } { { "DDS.bdf" "inst2" { Schematic "F:/Projects/VHDL/DDS/DDS.bdf" { { -104 296 456 -8 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom lpm_rom_juchi:inst2\|lpm_rom:lpm_rom_component " "Info: Elaborating entity \"lpm_rom\" for hierarchy \"lpm_rom_juchi:inst2\|lpm_rom:lpm_rom_component\"" {  } { { "lpm_rom_juchi.tdf" "lpm_rom_component" { Text "F:/Projects/VHDL/DDS/lpm_rom_juchi.tdf" 46 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altrom lpm_rom_juchi:inst2\|lpm_rom:lpm_rom_component\|altrom:srom " "Info: Elaborating entity \"altrom\" for hierarchy \"lpm_rom_juchi:inst2\|lpm_rom:lpm_rom_component\|altrom:srom\"" {  } { { "lpm_rom.tdf" "srom" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_rom.tdf" 52 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_rom_sanjiao.vhd 2 1 " "Warning: Using design file lpm_rom_sanjiao.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_rom_sanjiao-SYN " "Info: Found design unit 1: lpm_rom_sanjiao-SYN" {  } { { "lpm_rom_sanjiao.vhd" "" { Text "F:/Projects/VHDL/DDS/lpm_rom_sanjiao.vhd" 50 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_rom_sanjiao " "Info: Found entity 1: lpm_rom_sanjiao" {  } { { "lpm_rom_sanjiao.vhd" "" { Text "F:/Projects/VHDL/DDS/lpm_rom_sanjiao.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom_sanjiao lpm_rom_sanjiao:inst3 " "Info: Elaborating entity \"lpm_rom_sanjiao\" for hierarchy \"lpm_rom_sanjiao:inst3\"" {  } { { "DDS.bdf" "inst3" { Schematic "F:/Projects/VHDL/DDS/DDS.bdf" { { -8 296 456 88 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom lpm_rom_sanjiao:inst3\|lpm_rom:lpm_rom_component " "Info: Elaborating entity \"lpm_rom\" for hierarchy \"lpm_rom_sanjiao:inst3\|lpm_rom:lpm_rom_component\"" {  } { { "lpm_rom_sanjiao.vhd" "lpm_rom_component" { Text "F:/Projects/VHDL/DDS/lpm_rom_sanjiao.vhd" 77 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altrom lpm_rom_sanjiao:inst3\|lpm_rom:lpm_rom_component\|altrom:srom " "Info: Elaborating entity \"altrom\" for hierarchy \"lpm_rom_sanjiao:inst3\|lpm_rom:lpm_rom_component\|altrom:srom\"" {  } { { "lpm_rom.tdf" "srom" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_rom.tdf" 52 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_rom_sin.vhd 2 1 " "Warning: Using design file lpm_rom_sin.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_rom_sin-SYN " "Info: Found design unit 1: lpm_rom_sin-SYN" {  } { { "lpm_rom_sin.vhd" "" { Text "F:/Projects/VHDL/DDS/lpm_rom_sin.vhd" 50 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_rom_sin " "Info: Found entity 1: lpm_rom_sin" {  } { { "lpm_rom_sin.vhd" "" { Text "F:/Projects/VHDL/DDS/lpm_rom_sin.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom_sin lpm_rom_sin:inst1 " "Info: Elaborating entity \"lpm_rom_sin\" for hierarchy \"lpm_rom_sin:inst1\"" {  } { { "DDS.bdf" "inst1" { Schematic "F:/Projects/VHDL/DDS/DDS.bdf" { { -200 296 456 -104 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom lpm_rom_sin:inst1\|lpm_rom:lpm_rom_component " "Info: Elaborating entity \"lpm_rom\" for hierarchy \"lpm_rom_sin:inst1\|lpm_rom:lpm_rom_component\"" {  } { { "lpm_rom_sin.vhd" "lpm_rom_component" { Text "F:/Projects/VHDL/DDS/lpm_rom_sin.vhd" 77 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altrom lpm_rom_sin:inst1\|lpm_rom:lpm_rom_component\|altrom:srom " "Info: Elaborating entity \"altrom\" for hierarchy \"lpm_rom_sin:inst1\|lpm_rom:lpm_rom_component\|altrom:srom\"" {  } { { "lpm_rom.tdf" "srom" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_rom.tdf" 52 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "PhaseAcc:inst\|PAREG\[5\] data_in GND " "Warning: Reduced register \"PhaseAcc:inst\|PAREG\[5\]\" with stuck data_in port to stuck value GND" {  } { { "PhaseAcc.vhd" "" { Text "F:/Projects/VHDL/DDS/PhaseAcc.vhd" 74 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "PhaseAcc:inst\|PAREG\[4\] data_in GND " "Warning: Reduced register \"PhaseAcc:inst\|PAREG\[4\]\" with stuck data_in port to stuck value GND" {  } { { "PhaseAcc.vhd" "" { Text "F:/Projects/VHDL/DDS/PhaseAcc.vhd" 74 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "PhaseAcc:inst\|PAREG\[3\] data_in GND " "Warning: Reduced register \"PhaseAcc:inst\|PAREG\[3\]\" with stuck data_in port to stuck value GND" {  } { { "PhaseAcc.vhd" "" { Text "F:/Projects/VHDL/DDS/PhaseAcc.vhd" 74 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "PhaseAcc:inst\|PAREG\[2\] data_in GND " "Warning: Reduced register \"PhaseAcc:inst\|PAREG\[2\]\" with stuck data_in port to stuck value GND" {  } { { "PhaseAcc.vhd" "" { Text "F:/Projects/VHDL/DDS/PhaseAcc.vhd" 74 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "PhaseAcc:inst\|PAREG\[1\] data_in GND " "Warning: Reduced register \"PhaseAcc:inst\|PAREG\[1\]\" with stuck data_in port to stuck value GND" {  } { { "PhaseAcc.vhd" "" { Text "F:/Projects/VHDL/DDS/PhaseAcc.vhd" 74 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "PhaseAcc:inst\|PAREG\[0\] data_in GND " "Warning: Reduced register \"PhaseAcc:inst\|PAREG\[0\]\" with stuck data_in port to stuck value GND" {  } { { "PhaseAcc.vhd" "" { Text "F:/Projects/VHDL/DDS/PhaseAcc.vhd" 74 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}