dds.map.qmsg

利用FPGA的资源实现任意波形的产生

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 05 13:49:44 2006 " "Info: Processing started: Thu Oct 05 13:49:44 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DDS -c DDS " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DDS -c DDS" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DDS.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file DDS.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 DDS " "Info: Found entity 1: DDS" {  } { { "DDS.bdf" "" { Schematic "F:/Projects/VHDL/DDS/DDS.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "PhaseAcc.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file PhaseAcc.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 PhaseAcc-PhaseAcc_architecture " "Info: Found design unit 1: PhaseAcc-PhaseAcc_architecture" {  } { { "PhaseAcc.vhd" "" { Text "F:/Projects/VHDL/DDS/PhaseAcc.vhd" 47 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 PhaseAcc " "Info: Found entity 1: PhaseAcc" {  } { { "PhaseAcc.vhd" "" { Text "F:/Projects/VHDL/DDS/PhaseAcc.vhd" 29 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "PathSel.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file PathSel.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 PathSel-PathSel_architecture " "Info: Found design unit 1: PathSel-PathSel_architecture" {  } { { "PathSel.vhd" "" { Text "F:/Projects/VHDL/DDS/PathSel.vhd" 47 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 PathSel " "Info: Found entity 1: PathSel" {  } { { "PathSel.vhd" "" { Text "F:/Projects/VHDL/DDS/PathSel.vhd" 29 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SUB.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file SUB.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 SUB-block_name_architecture " "Info: Found design unit 1: SUB-block_name_architecture" {  } { { "SUB.vhd" "" { Text "F:/Projects/VHDL/DDS/SUB.vhd" 43 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 SUB " "Info: Found entity 1: SUB" {  } { { "SUB.vhd" "" { Text "F:/Projects/VHDL/DDS/SUB.vhd" 29 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "DDS " "Info: Elaborating entity \"DDS\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SUB SUB:inst6 " "Info: Elaborating entity \"SUB\" for hierarchy \"SUB:inst6\"" {  } { { "DDS.bdf" "inst6" { Schematic "F:/Projects/VHDL/DDS/DDS.bdf" { { -280 696 880 -168 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "PathSel PathSel:inst5 " "Info: Elaborating entity \"PathSel\" for hierarchy \"PathSel:inst5\"" {  } { { "DDS.bdf" "inst5" { Schematic "F:/Projects/VHDL/DDS/DDS.bdf" { { -328 488 696 -168 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_rom_fangbo.vhd 2 1 " "Warning: Using design file lpm_rom_fangbo.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_rom_fangbo-SYN " "Info: Found design unit 1: lpm_rom_fangbo-SYN" {  } { { "lpm_rom_fangbo.vhd" "" { Text "F:/Projects/VHDL/DDS/lpm_rom_fangbo.vhd" 50 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_rom_fangbo " "Info: Found entity 1: lpm_rom_fangbo" {  } { { "lpm_rom_fangbo.vhd" "" { Text "F:/Projects/VHDL/DDS/lpm_rom_fangbo.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom_fangbo lpm_rom_fangbo:inst4 " "Info: Elaborating entity \"lpm_rom_fangbo\" for hierarchy \"lpm_rom_fangbo:inst4\"" {  } { { "DDS.bdf" "inst4" { Schematic "F:/Projects/VHDL/DDS/DDS.bdf" { { 88 296 456 184 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51/libraries/megafunctions/lpm_rom.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/lpm_rom.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_rom " "Info: Found entity 1: lpm_rom" {  } { { "lpm_rom.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_rom.tdf" 41 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom lpm_rom_fangbo:inst4\|lpm_rom:lpm_rom_component " "Info: Elaborating entity \"lpm_rom\" for hierarchy \"lpm_rom_fangbo:inst4\|lpm_rom:lpm_rom_component\"" {  } { { "lpm_rom_fangbo.vhd" "lpm_rom_component" { Text "F:/Projects/VHDL/DDS/lpm_rom_fangbo.vhd" 77 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51/libraries/megafunctions/altrom.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/altrom.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altrom " "Info: Found entity 1: altrom" {  } { { "altrom.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/altrom.tdf" 75 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altrom lpm_rom_fangbo:inst4\|lpm_rom:lpm_rom_component\|altrom:srom " "Info: Elaborating entity \"altrom\" for hierarchy \"lpm_rom_fangbo:inst4\|lpm_rom:lpm_rom_component\|altrom:srom\"" {  } { { "lpm_rom.tdf" "srom" { Text "d:/altera/quartus51/libraries/megafunctions/lpm_rom.tdf" 52 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "PhaseAcc PhaseAcc:inst " "Info: Elaborating entity \"PhaseAcc\" for hierarchy \"PhaseAcc:inst\"" {  } { { "DDS.bdf" "inst" { Schematic "F:/Projects/VHDL/DDS/DDS.bdf" { { -328 264 488 -208 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "PhaseAcc PhaseAcc.vhd(49) " "Info (10035): Verilog HDL or VHDL information at PhaseAcc.vhd(49): object \"PhaseAcc\" declared but not used" {  } { { "PhaseAcc.vhd" "" { Text "F:/Projects/VHDL/DDS/PhaseAcc.vhd" 49 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}