dds.tan.qmsg

利用FPGA的资源实现任意波形的产生

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "FreInc register PhaseAcc:inst\|PASTEP\[7\] register PhaseAcc:inst\|PASTEP\[23\] 178.57 MHz 5.6 ns Internal " "Info: Clock \"FreInc\" has Internal fmax of 178.57 MHz between source register \"PhaseAcc:inst\|PASTEP\[7\]\" and destination register \"PhaseAcc:inst\|PASTEP\[23\]\" (period= 5.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.700 ns + Longest register register " "Info: + Longest register to register delay is 4.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PhaseAcc:inst\|PASTEP\[7\] 1 REG LC3_D30 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_D30; Fanout = 6; REG Node = 'PhaseAcc:inst\|PASTEP\[7\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "" { PhaseAcc:inst|PASTEP[7] } "NODE_NAME" } "" } } { "PhaseAcc.vhd" "" { Text "F:/Projects/VHDL/DDS/PhaseAcc.vhd" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(0.400 ns) 1.100 ns PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\] 2 COMB LC5_D29 2 " "Info: 2: + IC(0.700 ns) + CELL(0.400 ns) = 1.100 ns; Loc. = LC5_D29; Fanout = 2; COMB Node = 'PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "1.100 ns" { PhaseAcc:inst|PASTEP[7] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[1] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.200 ns PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\] 3 COMB LC6_D29 2 " "Info: 3: + IC(0.000 ns) + CELL(0.100 ns) = 1.200 ns; Loc. = LC6_D29; Fanout = 2; COMB Node = 'PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "0.100 ns" { PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[1] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[2] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\] 4 COMB LC7_D29 2 " "Info: 4: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC7_D29; Fanout = 2; COMB Node = 'PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "0.100 ns" { PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[2] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[3] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.400 ns PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\] 5 COMB LC8_D29 2 " "Info: 5: + IC(0.000 ns) + CELL(0.100 ns) = 1.400 ns; Loc. = LC8_D29; Fanout = 2; COMB Node = 'PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "0.100 ns" { PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[3] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[4] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.100 ns) 1.600 ns PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\] 6 COMB LC1_D31 2 " "Info: 6: + IC(0.100 ns) + CELL(0.100 ns) = 1.600 ns; Loc. = LC1_D31; Fanout = 2; COMB Node = 'PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "0.200 ns" { PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[4] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[5] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.700 ns PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\] 7 COMB LC2_D31 2 " "Info: 7: + IC(0.000 ns) + CELL(0.100 ns) = 1.700 ns; Loc. = LC2_D31; Fanout = 2; COMB Node = 'PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "0.100 ns" { PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[5] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[6] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.800 ns PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[7\] 8 COMB LC3_D31 2 " "Info: 8: + IC(0.000 ns) + CELL(0.100 ns) = 1.800 ns; Loc. = LC3_D31; Fanout = 2; COMB Node = 'PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[7\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "0.100 ns" { PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[6] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[7] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.900 ns PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[8\] 9 COMB LC4_D31 2 " "Info: 9: + IC(0.000 ns) + CELL(0.100 ns) = 1.900 ns; Loc. = LC4_D31; Fanout = 2; COMB Node = 'PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[8\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "0.100 ns" { PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[7] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[8] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 2.000 ns PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[9\] 10 COMB LC5_D31 2 " "Info: 10: + IC(0.000 ns) + CELL(0.100 ns) = 2.000 ns; Loc. = LC5_D31; Fanout = 2; COMB Node = 'PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[9\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "0.100 ns" { PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[8] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[9] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 2.100 ns PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[10\] 11 COMB LC6_D31 2 " "Info: 11: + IC(0.000 ns) + CELL(0.100 ns) = 2.100 ns; Loc. = LC6_D31; Fanout = 2; COMB Node = 'PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[10\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "0.100 ns" { PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[9] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[10] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 2.200 ns PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[11\] 12 COMB LC7_D31 2 " "Info: 12: + IC(0.000 ns) + CELL(0.100 ns) = 2.200 ns; Loc. = LC7_D31; Fanout = 2; COMB Node = 'PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[11\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "0.100 ns" { PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[10] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[11] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 2.300 ns PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[12\] 13 COMB LC8_D31 2 " "Info: 13: + IC(0.000 ns) + CELL(0.100 ns) = 2.300 ns; Loc. = LC8_D31; Fanout = 2; COMB Node = 'PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[12\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "0.100 ns" { PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[11] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[12] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.100 ns) 2.500 ns PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[13\] 14 COMB LC1_D33 2 " "Info: 14: + IC(0.100 ns) + CELL(0.100 ns) = 2.500 ns; Loc. = LC1_D33; Fanout = 2; COMB Node = 'PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[13\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "0.200 ns" { PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[12] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[13] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 2.600 ns PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[14\] 15 COMB LC2_D33 2 " "Info: 15: + IC(0.000 ns) + CELL(0.100 ns) = 2.600 ns; Loc. = LC2_D33; Fanout = 2; COMB Node = 'PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[14\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "0.100 ns" { PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[13] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[14] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 2.700 ns PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[15\] 16 COMB LC3_D33 2 " "Info: 16: + IC(0.000 ns) + CELL(0.100 ns) = 2.700 ns; Loc. = LC3_D33; Fanout = 2; COMB Node = 'PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[15\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "0.100 ns" { PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[14] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[15] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 2.800 ns PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[16\] 17 COMB LC4_D33 1 " "Info: 17: + IC(0.000 ns) + CELL(0.100 ns) = 2.800 ns; Loc. = LC4_D33; Fanout = 1; COMB Node = 'PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[16\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "0.100 ns" { PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[15] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[16] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 3.600 ns PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|unreg_res_node\[17\] 18 COMB LC5_D33 1 " "Info: 18: + IC(0.000 ns) + CELL(0.800 ns) = 3.600 ns; Loc. = LC5_D33; Fanout = 1; COMB Node = 'PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|unreg_res_node\[17\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "0.800 ns" { PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[16] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|unreg_res_node[17] } "NODE_NAME" } "" } } { "addcore.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/addcore.tdf" 95 16 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.500 ns) 4.700 ns PhaseAcc:inst\|PASTEP\[23\] 19 REG LC6_D34 3 " "Info: 19: + IC(0.600 ns) + CELL(0.500 ns) = 4.700 ns; Loc. = LC6_D34; Fanout = 3; REG Node = 'PhaseAcc:inst\|PASTEP\[23\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "1.100 ns" { PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|unreg_res_node[17] PhaseAcc:inst|PASTEP[23] } "NODE_NAME" } "" } } { "PhaseAcc.vhd" "" { Text "F:/Projects/VHDL/DDS/PhaseAcc.vhd" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns ( 68.09 % ) " "Info: Total cell delay = 3.200 ns ( 68.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.500 ns ( 31.91 % ) " "Info: Total interconnect delay = 1.500 ns ( 31.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "4.700 ns" { PhaseAcc:inst|PASTEP[7] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[1] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[2] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[3] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[4] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[5] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[6] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[7] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[8] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[9] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[10] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[11] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[12] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[13] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[14] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[15] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[16] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|unreg_res_node[17] PhaseAcc:inst|PASTEP[23] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.700 ns" { PhaseAcc:inst|PASTEP[7] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[1] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[2] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[3] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[4] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[5] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[6] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[7] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[8] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[9] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[10] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[11] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[12] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[13] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[14] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[15] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[16] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|unreg_res_node[17] PhaseAcc:inst|PASTEP[23] } { 0.000ns 0.700ns 0.000ns 0.000ns 0.000ns 0.100ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.100ns 0.000ns 0.000ns 0.000ns 0.000ns 0.600ns } { 0.000ns 0.400ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.800ns 0.500ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.200 ns - Smallest " "Info: - Smallest clock skew is 0.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "FreInc destination 5.800 ns + Shortest register " "Info: + Shortest clock path from clock \"FreInc\" to destination register is 5.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns FreInc 1 CLK PIN_12 3 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_12; Fanout = 3; CLK Node = 'FreInc'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "" { FreInc } "NODE_NAME" } "" } } { "DDS.bdf" "" { Schematic "F:/Projects/VHDL/DDS/DDS.bdf" { { -264 32 200 -248 "FreInc" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(0.800 ns) 4.800 ns PhaseAcc:inst\|EVENTCHECK 2 COMB LC1_D29 19 " "Info: 2: + IC(1.800 ns) + CELL(0.800 ns) = 4.800 ns; Loc. = LC1_D29; Fanout = 19; COMB Node = 'PhaseAcc:inst\|EVENTCHECK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "2.600 ns" { FreInc PhaseAcc:inst|EVENTCHECK } "NODE_NAME" } "" } } { "PhaseAcc.vhd" "" { Text "F:/Projects/VHDL/DDS/PhaseAcc.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.000 ns) 5.800 ns PhaseAcc:inst\|PASTEP\[23\] 3 REG LC6_D34 3 " "Info: 3: + IC(1.000 ns) + CELL(0.000 ns) = 5.800 ns; Loc. = LC6_D34; Fanout = 3; REG Node = 'PhaseAcc:inst\|PASTEP\[23\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "1.000 ns" { PhaseAcc:inst|EVENTCHECK PhaseAcc:inst|PASTEP[23] } "NODE_NAME" } "" } } { "PhaseAcc.vhd" "" { Text "F:/Projects/VHDL/DDS/PhaseAcc.vhd" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 51.72 % ) " "Info: Total cell delay = 3.000 ns ( 51.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns ( 48.28 % ) " "Info: Total interconnect delay = 2.800 ns ( 48.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "5.800 ns" { FreInc PhaseAcc:inst|EVENTCHECK PhaseAcc:inst|PASTEP[23] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.800 ns" { FreInc FreInc~out PhaseAcc:inst|EVENTCHECK PhaseAcc:inst|PASTEP[23] } { 0.000ns 0.000ns 1.800ns 1.000ns } { 0.000ns 2.200ns 0.800ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "FreInc source 5.600 ns - Longest register " "Info: - Longest clock path from clock \"FreInc\" to source register is 5.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns FreInc 1 CLK PIN_12 3 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_12; Fanout = 3; CLK Node = 'FreInc'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "" { FreInc } "NODE_NAME" } "" } } { "DDS.bdf" "" { Schematic "F:/Projects/VHDL/DDS/DDS.bdf" { { -264 32 200 -248 "FreInc" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(0.800 ns) 4.800 ns PhaseAcc:inst\|EVENTCHECK 2 COMB LC1_D29 19 " "Info: 2: + IC(1.800 ns) + CELL(0.800 ns) = 4.800 ns; Loc. = LC1_D29; Fanout = 19; COMB Node = 'PhaseAcc:inst\|EVENTCHECK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "2.600 ns" { FreInc PhaseAcc:inst|EVENTCHECK } "NODE_NAME" } "" } } { "PhaseAcc.vhd" "" { Text "F:/Projects/VHDL/DDS/PhaseAcc.vhd" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(0.000 ns) 5.600 ns PhaseAcc:inst\|PASTEP\[7\] 3 REG LC3_D30 6 " "Info: 3: + IC(0.800 ns) + CELL(0.000 ns) = 5.600 ns; Loc. = LC3_D30; Fanout = 6; REG Node = 'PhaseAcc:inst\|PASTEP\[7\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "0.800 ns" { PhaseAcc:inst|EVENTCHECK PhaseAcc:inst|PASTEP[7] } "NODE_NAME" } "" } } { "PhaseAcc.vhd" "" { Text "F:/Projects/VHDL/DDS/PhaseAcc.vhd" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 53.57 % ) " "Info: Total cell delay = 3.000 ns ( 53.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns ( 46.43 % ) " "Info: Total interconnect delay = 2.600 ns ( 46.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "5.600 ns" { FreInc PhaseAcc:inst|EVENTCHECK PhaseAcc:inst|PASTEP[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.600 ns" { FreInc FreInc~out PhaseAcc:inst|EVENTCHECK PhaseAcc:inst|PASTEP[7] } { 0.000ns 0.000ns 1.800ns 0.800ns } { 0.000ns 2.200ns 0.800ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "5.800 ns" { FreInc PhaseAcc:inst|EVENTCHECK PhaseAcc:inst|PASTEP[23] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.800 ns" { FreInc FreInc~out PhaseAcc:inst|EVENTCHECK PhaseAcc:inst|PASTEP[23] } { 0.000ns 0.000ns 1.800ns 1.000ns } { 0.000ns 2.200ns 0.800ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "5.600 ns" { FreInc PhaseAcc:inst|EVENTCHECK PhaseAcc:inst|PASTEP[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.600 ns" { FreInc FreInc~out PhaseAcc:inst|EVENTCHECK PhaseAcc:inst|PASTEP[7] } { 0.000ns 0.000ns 1.800ns 0.800ns } { 0.000ns 2.200ns 0.800ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.600 ns + " "Info: + Micro clock to output delay of source is 0.600 ns" {  } { { "PhaseAcc.vhd" "" { Text "F:/Projects/VHDL/DDS/PhaseAcc.vhd" 62 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.500 ns + " "Info: + Micro setup delay of destination is 0.500 ns" {  } { { "PhaseAcc.vhd" "" { Text "F:/Projects/VHDL/DDS/PhaseAcc.vhd" 62 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "4.700 ns" { PhaseAcc:inst|PASTEP[7] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[1] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[2] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[3] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[4] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[5] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[6] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[7] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[8] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[9] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[10] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[11] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[12] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[13] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[14] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[15] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[16] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|unreg_res_node[17] PhaseAcc:inst|PASTEP[23] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.700 ns" { PhaseAcc:inst|PASTEP[7] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[1] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[2] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[3] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[4] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[5] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[6] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[7] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[8] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[9] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[10] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[11] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[12] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[13] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[14] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[15] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[16] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|unreg_res_node[17] PhaseAcc:inst|PASTEP[23] } { 0.000ns 0.700ns 0.000ns 0.000ns 0.000ns 0.100ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.100ns 0.000ns 0.000ns 0.000ns 0.000ns 0.600ns } { 0.000ns 0.400ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.100ns 0.800ns 0.500ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "5.800 ns" { FreInc PhaseAcc:inst|EVENTCHECK PhaseAcc:inst|PASTEP[23] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.800 ns" { FreInc FreInc~out PhaseAcc:inst|EVENTCHECK PhaseAcc:inst|PASTEP[23] } { 0.000ns 0.000ns 1.800ns 1.000ns } { 0.000ns 2.200ns 0.800ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "5.600 ns" { FreInc PhaseAcc:inst|EVENTCHECK PhaseAcc:inst|PASTEP[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.600 ns" { FreInc FreInc~out PhaseAcc:inst|EVENTCHECK PhaseAcc:inst|PASTEP[7] } { 0.000ns 0.000ns 1.800ns 0.800ns } { 0.000ns 2.200ns 0.800ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "FreDec register PhaseAcc:inst\|PASTEP\[7\] register PhaseAcc:inst\|PASTEP\[23\] 178.57 MHz 5.6 ns Internal " "Info: Clock \"FreDec\" has Internal fmax of 178.57 MHz between source register \"PhaseAcc:inst\|PASTEP\[7\]\" and destination register \"PhaseAcc:inst\|PASTEP\[23\]\" (period= 5.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.700 ns + Longest register register " "Info: + Longest register to register delay is 4.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PhaseAcc:inst\|PASTEP\[7\] 1 REG LC3_D30 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_D30; Fanout = 6; REG Node = 'PhaseAcc:inst\|PASTEP\[7\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "" { PhaseAcc:inst|PASTEP[7] } "NODE_NAME" } "" } } { "PhaseAcc.vhd" "" { Text "F:/Projects/VHDL/DDS/PhaseAcc.vhd" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(0.400 ns) 1.100 ns PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\] 2 COMB LC5_D29 2 " "Info: 2: + IC(0.700 ns) + CELL(0.400 ns) = 1.100 ns; Loc. = LC5_D29; Fanout = 2; COMB Node = 'PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "1.100 ns" { PhaseAcc:inst|PASTEP[7] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[1] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.200 ns PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\] 3 COMB LC6_D29 2 " "Info: 3: + IC(0.000 ns) + CELL(0.100 ns) = 1.200 ns; Loc. = LC6_D29; Fanout = 2; COMB Node = 'PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "0.100 ns" { PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[1] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[2] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\] 4 COMB LC7_D29 2 " "Info: 4: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC7_D29; Fanout = 2; COMB Node = 'PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "0.100 ns" { PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[2] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[3] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.400 ns PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\] 5 COMB LC8_D29 2 " "Info: 5: + IC(0.000 ns) + CELL(0.100 ns) = 1.400 ns; Loc. = LC8_D29; Fanout = 2; COMB Node = 'PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "0.100 ns" { PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[3] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[4] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.100 ns) 1.600 ns PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\] 6 COMB LC1_D31 2 " "Info: 6: + IC(0.100 ns) + CELL(0.100 ns) = 1.600 ns; Loc. = LC1_D31; Fanout = 2; COMB Node = 'PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "0.200 ns" { PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[4] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[5] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.700 ns PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\] 7 COMB LC2_D31 2 " "Info: 7: + IC(0.000 ns) + CELL(0.100 ns) = 1.700 ns; Loc. = LC2_D31; Fanout = 2; COMB Node = 'PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "0.100 ns" { PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[5] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[6] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.800 ns PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[7\] 8 COMB LC3_D31 2 " "Info: 8: + IC(0.000 ns) + CELL(0.100 ns) = 1.800 ns; Loc. = LC3_D31; Fanout = 2; COMB Node = 'PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[7\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "0.100 ns" { PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[6] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[7] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.900 ns PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[8\] 9 COMB LC4_D31 2 " "Info: 9: + IC(0.000 ns) + CELL(0.100 ns) = 1.900 ns; Loc. = LC4_D31; Fanout = 2; COMB Node = 'PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[8\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "0.100 ns" { PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[7] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[8] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 2.000 ns PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[9\] 10 COMB LC5_D31 2 " "Info: 10: + IC(0.000 ns) + CELL(0.100 ns) = 2.000 ns; Loc. = LC5_D31; Fanout = 2; COMB Node = 'PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[9\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "0.100 ns" { PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[8] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[9] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 2.100 ns PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[10\] 11 COMB LC6_D31 2 " "Info: 11: + IC(0.000 ns) + CELL(0.100 ns) = 2.100 ns; Loc. = LC6_D31; Fanout = 2; COMB Node = 'PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[10\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "0.100 ns" { PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[9] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[10] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 2.200 ns PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[11\] 12 COMB LC7_D31 2 " "Info: 12: + IC(0.000 ns) + CELL(0.100 ns) = 2.200 ns; Loc. = LC7_D31; Fanout = 2; COMB Node = 'PhaseAcc:inst\|lpm_add_sub:add_rtl_5\|addcore:adder\|a_csnbuffer:result_node\|cout\[11\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "0.100 ns" { PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[10] PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[11] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!;