dds.tan.qmsg

利用FPGA的资源实现任意波形的产生

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "PhaseAcc:inst\|EVENTCHECK " "Info: Detected gated clock \"PhaseAcc:inst\|EVENTCHECK\" as buffer" {  } { { "PhaseAcc.vhd" "" { Text "F:/Projects/VHDL/DDS/PhaseAcc.vhd" 54 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PhaseAcc:inst\|EVENTCHECK" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "PhaseAcc:inst\|FP2 " "Info: Detected ripple clock \"PhaseAcc:inst\|FP2\" as buffer" {  } { { "PhaseAcc.vhd" "" { Text "F:/Projects/VHDL/DDS/PhaseAcc.vhd" 82 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "PhaseAcc:inst\|FP2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register PhaseAcc:inst\|PAREG\[22\] memory lpm_rom_juchi:inst2\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[4\]~reg_ra4 147.06 MHz 6.8 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 147.06 MHz between source register \"PhaseAcc:inst\|PAREG\[22\]\" and destination memory \"lpm_rom_juchi:inst2\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[4\]~reg_ra4\" (period= 6.8 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.100 ns + Longest register memory " "Info: + Longest register to memory delay is 2.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PhaseAcc:inst\|PAREG\[22\] 1 REG LC1_D13 26 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_D13; Fanout = 26; REG Node = 'PhaseAcc:inst\|PAREG\[22\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "" { PhaseAcc:inst|PAREG[22] } "NODE_NAME" } "" } } { "PhaseAcc.vhd" "" { Text "F:/Projects/VHDL/DDS/PhaseAcc.vhd" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.500 ns) 2.100 ns lpm_rom_juchi:inst2\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[4\]~reg_ra4 2 MEM EC16_D 1 " "Info: 2: + IC(1.600 ns) + CELL(0.500 ns) = 2.100 ns; Loc. = EC16_D; Fanout = 1; MEM Node = 'lpm_rom_juchi:inst2\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[4\]~reg_ra4'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "2.100 ns" { PhaseAcc:inst|PAREG[22] lpm_rom_juchi:inst2|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra4 } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 23.81 % ) " "Info: Total cell delay = 0.500 ns ( 23.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 76.19 % ) " "Info: Total interconnect delay = 1.600 ns ( 76.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "2.100 ns" { PhaseAcc:inst|PAREG[22] lpm_rom_juchi:inst2|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra4 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.100 ns" { PhaseAcc:inst|PAREG[22] lpm_rom_juchi:inst2|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra4 } { 0.000ns 1.600ns } { 0.000ns 0.500ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 6.200 ns + Shortest memory " "Info: + Shortest clock path from clock \"CLK\" to destination memory is 6.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns CLK 1 CLK PIN_55 1 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_55; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "" { CLK } "NODE_NAME" } "" } } { "DDS.bdf" "" { Schematic "F:/Projects/VHDL/DDS/DDS.bdf" { { -336 32 200 -320 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(0.600 ns) 2.800 ns PhaseAcc:inst\|FP2 2 REG LC1_J24 187 " "Info: 2: + IC(0.800 ns) + CELL(0.600 ns) = 2.800 ns; Loc. = LC1_J24; Fanout = 187; REG Node = 'PhaseAcc:inst\|FP2'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "1.400 ns" { CLK PhaseAcc:inst|FP2 } "NODE_NAME" } "" } } { "PhaseAcc.vhd" "" { Text "F:/Projects/VHDL/DDS/PhaseAcc.vhd" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(0.000 ns) 6.200 ns lpm_rom_juchi:inst2\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[4\]~reg_ra4 3 MEM EC16_D 1 " "Info: 3: + IC(3.400 ns) + CELL(0.000 ns) = 6.200 ns; Loc. = EC16_D; Fanout = 1; MEM Node = 'lpm_rom_juchi:inst2\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[4\]~reg_ra4'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "3.400 ns" { PhaseAcc:inst|FP2 lpm_rom_juchi:inst2|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra4 } "NODE_NAME" } "" } } { "altrom.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 32.26 % ) " "Info: Total cell delay = 2.000 ns ( 32.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.200 ns ( 67.74 % ) " "Info: Total interconnect delay = 4.200 ns ( 67.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "6.200 ns" { CLK PhaseAcc:inst|FP2 lpm_rom_juchi:inst2|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra4 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.200 ns" { CLK CLK~out PhaseAcc:inst|FP2 lpm_rom_juchi:inst2|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra4 } { 0.000ns 0.000ns 0.800ns 3.400ns } { 0.000ns 1.400ns 0.600ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 6.200 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 6.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns CLK 1 CLK PIN_55 1 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_55; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "" { CLK } "NODE_NAME" } "" } } { "DDS.bdf" "" { Schematic "F:/Projects/VHDL/DDS/DDS.bdf" { { -336 32 200 -320 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(0.600 ns) 2.800 ns PhaseAcc:inst\|FP2 2 REG LC1_J24 187 " "Info: 2: + IC(0.800 ns) + CELL(0.600 ns) = 2.800 ns; Loc. = LC1_J24; Fanout = 187; REG Node = 'PhaseAcc:inst\|FP2'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "1.400 ns" { CLK PhaseAcc:inst|FP2 } "NODE_NAME" } "" } } { "PhaseAcc.vhd" "" { Text "F:/Projects/VHDL/DDS/PhaseAcc.vhd" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(0.000 ns) 6.200 ns PhaseAcc:inst\|PAREG\[22\] 3 REG LC1_D13 26 " "Info: 3: + IC(3.400 ns) + CELL(0.000 ns) = 6.200 ns; Loc. = LC1_D13; Fanout = 26; REG Node = 'PhaseAcc:inst\|PAREG\[22\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "3.400 ns" { PhaseAcc:inst|FP2 PhaseAcc:inst|PAREG[22] } "NODE_NAME" } "" } } { "PhaseAcc.vhd" "" { Text "F:/Projects/VHDL/DDS/PhaseAcc.vhd" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.000 ns ( 32.26 % ) " "Info: Total cell delay = 2.000 ns ( 32.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.200 ns ( 67.74 % ) " "Info: Total interconnect delay = 4.200 ns ( 67.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "6.200 ns" { CLK PhaseAcc:inst|FP2 PhaseAcc:inst|PAREG[22] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.200 ns" { CLK CLK~out PhaseAcc:inst|FP2 PhaseAcc:inst|PAREG[22] } { 0.000ns 0.000ns 0.800ns 3.400ns } { 0.000ns 1.400ns 0.600ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "6.200 ns" { CLK PhaseAcc:inst|FP2 lpm_rom_juchi:inst2|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra4 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.200 ns" { CLK CLK~out PhaseAcc:inst|FP2 lpm_rom_juchi:inst2|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra4 } { 0.000ns 0.000ns 0.800ns 3.400ns } { 0.000ns 1.400ns 0.600ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "6.200 ns" { CLK PhaseAcc:inst|FP2 PhaseAcc:inst|PAREG[22] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.200 ns" { CLK CLK~out PhaseAcc:inst|FP2 PhaseAcc:inst|PAREG[22] } { 0.000ns 0.000ns 0.800ns 3.400ns } { 0.000ns 1.400ns 0.600ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.600 ns + " "Info: + Micro clock to output delay of source is 0.600 ns" {  } { { "PhaseAcc.vhd" "" { Text "F:/Projects/VHDL/DDS/PhaseAcc.vhd" 74 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "altrom.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "PhaseAcc.vhd" "" { Text "F:/Projects/VHDL/DDS/PhaseAcc.vhd" 74 -1 0 } } { "altrom.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/altrom.tdf" 80 2 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "2.100 ns" { PhaseAcc:inst|PAREG[22] lpm_rom_juchi:inst2|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra4 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.100 ns" { PhaseAcc:inst|PAREG[22] lpm_rom_juchi:inst2|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra4 } { 0.000ns 1.600ns } { 0.000ns 0.500ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "6.200 ns" { CLK PhaseAcc:inst|FP2 lpm_rom_juchi:inst2|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra4 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.200 ns" { CLK CLK~out PhaseAcc:inst|FP2 lpm_rom_juchi:inst2|lpm_rom:lpm_rom_component|altrom:srom|q[4]~reg_ra4 } { 0.000ns 0.000ns 0.800ns 3.400ns } { 0.000ns 1.400ns 0.600ns 0.000ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "DDS" "UNKNOWN" "V1" "F:/Projects/VHDL/DDS/db/DDS.quartus_db" { Floorplan "F:/Projects/VHDL/DDS/" "" "6.200 ns" { CLK PhaseAcc:inst|FP2 PhaseAcc:inst|PAREG[22] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.200 ns" { CLK CLK~out PhaseAcc:inst|FP2 PhaseAcc:inst|PAREG[22] } { 0.000ns 0.000ns 0.800ns 3.400ns } { 0.000ns 1.400ns 0.600ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}