dds.tan.qmsg

利用FPGA的资源实现任意波形的产生

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "DDS.bdf" "" { Schematic "F:/Projects/VHDL/DDS/DDS.bdf" { { -336 32 200 -320 "CLK" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "FreInc " "Info: Assuming node \"FreInc\" is an undefined clock" {  } { { "DDS.bdf" "" { Schematic "F:/Projects/VHDL/DDS/DDS.bdf" { { -264 32 200 -248 "FreInc" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "FreInc" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "FreDec " "Info: Assuming node \"FreDec\" is an undefined clock" {  } { { "DDS.bdf" "" { Schematic "F:/Projects/VHDL/DDS/DDS.bdf" { { -288 32 200 -272 "FreDec" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "FreDec" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}