dds.fnsim.qmsg

利用FPGA的资源实现任意波形的产生

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom_juchi lpm_rom_juchi:inst2 " "Info: Elaborating entity \"lpm_rom_juchi\" for hierarchy \"lpm_rom_juchi:inst2\"" {  } { { "DDS.bdf" "inst2" { Schematic "F:/Projects/VHDL/DDS/DDS.bdf" { { -104 296 456 -8 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom lpm_rom_juchi:inst2\|lpm_rom:lpm_rom_component " "Info: Elaborating entity \"lpm_rom\" for hierarchy \"lpm_rom_juchi:inst2\|lpm_rom:lpm_rom_component\"" {  } { { "lpm_rom_juchi.tdf" "lpm_rom_component" { Text "F:/Projects/VHDL/DDS/lpm_rom_juchi.tdf" 46 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altrom lpm_rom_juchi:inst2\|lpm_rom:lpm_rom_component\|altrom:srom " "Info: Elaborating entity \"altrom\" for hierarchy \"lpm_rom_juchi:inst2\|lpm_rom:lpm_rom_component\|altrom:srom\"" {  } { { "lpm_rom.tdf" "srom" { Text "d:/program files/altera/quartus51/libraries/megafunctions/lpm_rom.tdf" 52 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_rom_sanjiao.vhd 2 1 " "Warning: Using design file lpm_rom_sanjiao.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_rom_sanjiao-SYN " "Info: Found design unit 1: lpm_rom_sanjiao-SYN" {  } { { "lpm_rom_sanjiao.vhd" "" { Text "F:/Projects/VHDL/DDS/lpm_rom_sanjiao.vhd" 50 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_rom_sanjiao " "Info: Found entity 1: lpm_rom_sanjiao" {  } { { "lpm_rom_sanjiao.vhd" "" { Text "F:/Projects/VHDL/DDS/lpm_rom_sanjiao.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom_sanjiao lpm_rom_sanjiao:inst3 " "Info: Elaborating entity \"lpm_rom_sanjiao\" for hierarchy \"lpm_rom_sanjiao:inst3\"" {  } { { "DDS.bdf" "inst3" { Schematic "F:/Projects/VHDL/DDS/DDS.bdf" { { -8 296 456 88 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom lpm_rom_sanjiao:inst3\|lpm_rom:lpm_rom_component " "Info: Elaborating entity \"lpm_rom\" for hierarchy \"lpm_rom_sanjiao:inst3\|lpm_rom:lpm_rom_component\"" {  } { { "lpm_rom_sanjiao.vhd" "lpm_rom_component" { Text "F:/Projects/VHDL/DDS/lpm_rom_sanjiao.vhd" 77 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altrom lpm_rom_sanjiao:inst3\|lpm_rom:lpm_rom_component\|altrom:srom " "Info: Elaborating entity \"altrom\" for hierarchy \"lpm_rom_sanjiao:inst3\|lpm_rom:lpm_rom_component\|altrom:srom\"" {  } { { "lpm_rom.tdf" "srom" { Text "d:/program files/altera/quartus51/libraries/megafunctions/lpm_rom.tdf" 52 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_rom_sin.vhd 2 1 " "Warning: Using design file lpm_rom_sin.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_rom_sin-SYN " "Info: Found design unit 1: lpm_rom_sin-SYN" {  } { { "lpm_rom_sin.vhd" "" { Text "F:/Projects/VHDL/DDS/lpm_rom_sin.vhd" 50 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_rom_sin " "Info: Found entity 1: lpm_rom_sin" {  } { { "lpm_rom_sin.vhd" "" { Text "F:/Projects/VHDL/DDS/lpm_rom_sin.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom_sin lpm_rom_sin:inst1 " "Info: Elaborating entity \"lpm_rom_sin\" for hierarchy \"lpm_rom_sin:inst1\"" {  } { { "DDS.bdf" "inst1" { Schematic "F:/Projects/VHDL/DDS/DDS.bdf" { { -200 296 456 -104 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom lpm_rom_sin:inst1\|lpm_rom:lpm_rom_component " "Info: Elaborating entity \"lpm_rom\" for hierarchy \"lpm_rom_sin:inst1\|lpm_rom:lpm_rom_component\"" {  } { { "lpm_rom_sin.vhd" "lpm_rom_component" { Text "F:/Projects/VHDL/DDS/lpm_rom_sin.vhd" 77 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altrom lpm_rom_sin:inst1\|lpm_rom:lpm_rom_component\|altrom:srom " "Info: Elaborating entity \"altrom\" for hierarchy \"lpm_rom_sin:inst1\|lpm_rom:lpm_rom_component\|altrom:srom\"" {  } { { "lpm_rom.tdf" "srom" { Text "d:/program files/altera/quartus51/libraries/megafunctions/lpm_rom.tdf" 52 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WCDB_CDB_MORE_INI_CONTENT" "64 65 " "Warning: Memory depth value (64) in design file differs from memory depth value (65) in Memory Initialization File -- truncated remaining initial content value to fit RAM" {  } { { "altrom.tdf" "" { Text "d:/program files/altera/quartus51/libraries/megafunctions/altrom.tdf" 127 13 0 } }  } 0 0 "Memory depth value (%1!d!) in design file differs from memory depth value (%2!d!) in Memory Initialization File -- truncated remaining initial content value to fit RAM" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "d:/program files/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus51/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus51/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "d:/program files/altera/quartus51/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus51/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus51/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "d:/program files/altera/quartus51/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 5 s Quartus II " "Info: Quartus II Functional Simulation Netlist Generation was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Sep 15 20:48:52 2006 " "Info: Processing ended: Fri Sep 15 20:48:52 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}