dds.sim.rpt

利用FPGA的资源实现任意波形的产生

+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+-------------------------------------------------------------------------+
; |DDS|lpm_rom_fangbo:inst4|lpm_rom:lpm_rom_component|altrom:srom|content ;
+-------------------------------------------------------------------------+
Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.


+--------------------------------------------------------------------------+
; |DDS|lpm_rom_sanjiao:inst3|lpm_rom:lpm_rom_component|altrom:srom|content ;
+--------------------------------------------------------------------------+
Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.


+----------------------------------------------------------------------+
; |DDS|lpm_rom_sin:inst1|lpm_rom:lpm_rom_component|altrom:srom|content ;
+----------------------------------------------------------------------+
Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.


+------------------------------------------------------------------------+
; |DDS|lpm_rom_juchi:inst2|lpm_rom:lpm_rom_component|altrom:srom|content ;
+------------------------------------------------------------------------+
Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.


+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      32.93 % ;
; Total nodes checked                                 ; 198          ;
; Total output ports checked                          ; 249          ;
; Total output ports with complete 1/0-value coverage ; 82           ;
; Total output ports with no 1/0-value coverage       ; 167          ;
; Total output ports with no 1-value coverage         ; 167          ;
; Total output ports with no 0-value coverage         ; 167          ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                                                          ;
+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                       ; Output Port Name                                                                                ; Output Port Type ;
+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+------------------+
; |DDS|PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~83  ; |DDS|PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~83  ; data_out0        ;
; |DDS|PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~90  ; |DDS|PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~90  ; data_out0        ;
; |DDS|PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~94  ; |DDS|PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~94  ; data_out0        ;
; |DDS|PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~98  ; |DDS|PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~98  ; data_out0        ;
; |DDS|PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~102 ; |DDS|PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~102 ; data_out0        ;
; |DDS|PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~106 ; |DDS|PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~106 ; data_out0        ;
; |DDS|PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~110 ; |DDS|PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~110 ; data_out0        ;
; |DDS|PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~114 ; |DDS|PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~114 ; data_out0        ;
; |DDS|PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~118 ; |DDS|PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~118 ; data_out0        ;
; |DDS|PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~122 ; |DDS|PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~122 ; data_out0        ;
; |DDS|PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~126 ; |DDS|PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~126 ; data_out0        ;
; |DDS|PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~129 ; |DDS|PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~129 ; data_out0        ;
; |DDS|PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~132 ; |DDS|PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~132 ; data_out0        ;
; |DDS|lpm_rom_fangbo:inst4|lpm_rom:lpm_rom_component|altrom:srom|q[5]                            ; |DDS|lpm_rom_fangbo:inst4|lpm_rom:lpm_rom_component|altrom:srom|q[5]                            ; dataout          ;
; |DDS|lpm_rom_fangbo:inst4|lpm_rom:lpm_rom_component|altrom:srom|q[4]                            ; |DDS|lpm_rom_fangbo:inst4|lpm_rom:lpm_rom_component|altrom:srom|q[4]                            ; dataout          ;
; |DDS|lpm_rom_fangbo:inst4|lpm_rom:lpm_rom_component|altrom:srom|q[3]                            ; |DDS|lpm_rom_fangbo:inst4|lpm_rom:lpm_rom_component|altrom:srom|q[3]                            ; dataout          ;
; |DDS|lpm_rom_fangbo:inst4|lpm_rom:lpm_rom_component|altrom:srom|q[2]                            ; |DDS|lpm_rom_fangbo:inst4|lpm_rom:lpm_rom_component|altrom:srom|q[2]                            ; dataout          ;
; |DDS|lpm_rom_fangbo:inst4|lpm_rom:lpm_rom_component|altrom:srom|q[1]                            ; |DDS|lpm_rom_fangbo:inst4|lpm_rom:lpm_rom_component|altrom:srom|q[1]                            ; dataout          ;
; |DDS|lpm_rom_fangbo:inst4|lpm_rom:lpm_rom_component|altrom:srom|q[0]                            ; |DDS|lpm_rom_fangbo:inst4|lpm_rom:lpm_rom_component|altrom:srom|q[0]                            ; dataout          ;
; |DDS|PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~131 ; |DDS|PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~131 ; data_out0        ;
; |DDS|PhaseAcc:inst|FP2                                                                          ; |DDS|PhaseAcc:inst|FP2                                                                          ; data_out0        ;
; |DDS|PhaseAcc:inst|PAREG[18]                                                                    ; |DDS|PhaseAcc:inst|PAREG[18]                                                                    ; data_out0        ;
; |DDS|PhaseAcc:inst|PAREG[19]                                                                    ; |DDS|PhaseAcc:inst|PAREG[19]                                                                    ; data_out0        ;
; |DDS|PhaseAcc:inst|PAREG[20]                                                                    ; |DDS|PhaseAcc:inst|PAREG[20]                                                                    ; data_out0        ;
; |DDS|PhaseAcc:inst|PAREG[21]                                                                    ; |DDS|PhaseAcc:inst|PAREG[21]                                                                    ; data_out0        ;
; |DDS|PhaseAcc:inst|PAREG[22]                                                                    ; |DDS|PhaseAcc:inst|PAREG[22]                                                                    ; data_out0        ;
; |DDS|PhaseAcc:inst|PAREG[23]                                                                    ; |DDS|PhaseAcc:inst|PAREG[23]                                                                    ; data_out0        ;
; |DDS|PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~139 ; |DDS|PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~139 ; data_out0        ;