phaseacc.vhd

利用FPGA的资源实现任意波形的产生

-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.

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-- Generated by Quartus II Version 6.0 (Build Build 178 04/27/2006)
-- Created on Mon Sep 11 20:23:12 2006

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

--  Entity Declaration

ENTITY PhaseAcc IS
	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	PORT
	(
		CLK : IN STD_LOGIC;
		RST : IN STD_LOGIC;
		FreDec : IN STD_LOGIC;
		FreInc : IN STD_LOGIC;
		ADCLK : OUT STD_LOGIC;
		addr : OUT STD_LOGIC_VECTOR(5 downto 0)
	);
	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	
END PhaseAcc;


--  Architecture Body

ARCHITECTURE PhaseAcc_architecture OF PhaseAcc IS

SIGNAL		PhaseAcc						:INTEGER RANGE 0 TO 2**6-1;
SIGNAL		FP2								:STD_LOGIC;	
SIGNAL		PAREG							:INTEGER RANGE 0 TO 2**24-1;
SIGNAL		PASTEP							:INTEGER RANGE 0 TO 2**24-1;
SIGNAL		address							:STD_LOGIC_VECTOR(23 DOWNTO 0);
SIGNAL		EVENTCHECK						:STD_LOGIC;
BEGIN
ADCLK<=FP2;
address(23 downto 0)<=CONV_STD_LOGIC_VECTOR(PAREG,24);
addr(5 downto 0)<=address(23 downto 18);
EVENTCHECK<=FreDec AND FreInc;
PROCESS(RST,EVENTCHECK)
BEGIN
	IF(RST='0')				THEN
		PASTEP<=2**18;
	ELSIF(EVENTCHECK'EVENT AND EVENTCHECK='0')				THEN
		IF(FreDec='0')				THEN
			PASTEP<=PASTEP-2**6;
		ELSIF(FreInc='0')			THEN
			PASTEP<=PASTEP+2**6;
		END IF;
	END IF;
END PROCESS;
PROCESS(FP2,RST)
BEGIN
	IF(RST='0')				THEN
		PAREG<=0;
	ELSIF(FP2'EVENT AND FP2='0')				THEN
		PAREG<=PAREG+PASTEP;
	END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
	IF(RST='0')				THEN
		FP2<='0';
	ELSIF(CLK'EVENT AND CLK='0')				THEN
		FP2<=NOT FP2;
	END IF;
END	PROCESS;
END PhaseAcc_architecture;