sub.vhd

利用FPGA的资源实现任意波形的产生

-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.


-- Generated by Quartus II Version 5.1 (Build Build 176 10/26/2005)
-- Created on Tue Sep 12 23:54:59 2006

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all; 
USE ieee.std_logic_unsigned.all;
--  Entity Declaration

ENTITY SUB IS
	-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
	PORT
	(
		AddOut : IN STD_LOGIC_VECTOR(7 downto 0);
		toda : OUT STD_LOGIC_VECTOR(7 downto 0)
	);
	-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
	
END SUB;


--  Architecture Body

ARCHITECTURE block_name_architecture OF SUB IS
SIGNAL		TEMP			:INTEGER RANGE -128 TO 128;
BEGIN
toda(7 downto 0)<=CONV_STD_LOGIC_VECTOR(TEMP,8);
TEMP<=CONV_INTEGER(AddOut(7 downto 0))-127;
END block_name_architecture;