dds.map.summary

利用FPGA的资源实现任意波形的产生

Analysis & Synthesis Status : Successful - Thu Oct 05 13:49:48 2006
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : DDS
Top-level Entity Name : DDS
Family : ACEX1K
Total logic elements : 158
Total pins : 16
Total memory bits : 1,536
Total PLLs : 0