dds.fit.eqn

利用FPGA的资源实现任意波形的产生

B1L68Q = B1_PASTEP[17];


--B1_PAREG[17] is PhaseAcc:inst|PAREG[17] at LC2_D19
--operation mode is normal

B1_PAREG[17]_lut_out = M11_cs_buffer[11];
B1_PAREG[17] = DFFEA(B1_PAREG[17]_lut_out, !GLOBAL(B1_FP2), GLOBAL(RST), , , , );

--B1L29Q is PhaseAcc:inst|PAREG[17]~76 at LC2_D19
--operation mode is normal

B1L29Q = B1_PAREG[17];


--M11_cs_buffer[10] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[10] at LC6_D16
--operation mode is arithmetic

M11_cs_buffer[10] = B1_PAREG[16] $ B1_PASTEP[16] $ M11_cout[9];

--M11L41 is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[10]~342 at LC6_D16
--operation mode is arithmetic

M11L41 = B1_PAREG[16] $ B1_PASTEP[16] $ M11_cout[9];

--M11_cout[10] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[10] at LC6_D16
--operation mode is arithmetic

M11_cout[10] = CARRY(B1_PAREG[16] & (B1_PASTEP[16] # M11_cout[9]) # !B1_PAREG[16] & B1_PASTEP[16] & M11_cout[9]);


--M14_cs_buffer[11] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[11] at LC7_D32
--operation mode is arithmetic

M14_cs_buffer[11] = B1_PASTEP[17] $ M14_cout[10];

--M14L44 is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[11]~228 at LC7_D32
--operation mode is arithmetic

M14L44 = B1_PASTEP[17] $ M14_cout[10];

--M14_cout[11] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[11] at LC7_D32
--operation mode is arithmetic

M14_cout[11] = CARRY(B1_PASTEP[17] & M14_cout[10]);


--M17_cs_buffer[11] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[11] at LC7_D31
--operation mode is arithmetic

M17_cs_buffer[11] = B1_PASTEP[17] $ M17_cout[10];

--M17L41 is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[11]~339 at LC7_D31
--operation mode is arithmetic

M17L41 = B1_PASTEP[17] $ M17_cout[10];

--M17_cout[11] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[11] at LC7_D31
--operation mode is arithmetic

M17_cout[11] = CARRY(B1_PASTEP[17] # M17_cout[10]);


--B1_PASTEP[16] is PhaseAcc:inst|PASTEP[16] at LC6_D28
--operation mode is normal

B1_PASTEP[16]_lut_out = FreDec & (M14_cs_buffer[10]) # !FreDec & !M17_cs_buffer[10];
B1_PASTEP[16] = DFFEA(B1_PASTEP[16]_lut_out, B1_EVENTCHECK, GLOBAL(RST), , , , );

--B1L66Q is PhaseAcc:inst|PASTEP[16]~379 at LC6_D28
--operation mode is normal

B1L66Q = B1_PASTEP[16];


--B1_PAREG[16] is PhaseAcc:inst|PAREG[16] at LC2_D7
--operation mode is normal

B1_PAREG[16]_lut_out = M11_cs_buffer[10];
B1_PAREG[16] = DFFEA(B1_PAREG[16]_lut_out, !GLOBAL(B1_FP2), GLOBAL(RST), , , , );

--B1L27Q is PhaseAcc:inst|PAREG[16]~77 at LC2_D7
--operation mode is normal

B1L27Q = B1_PAREG[16];


--M11_cs_buffer[9] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[9] at LC5_D16
--operation mode is arithmetic

M11_cs_buffer[9] = B1_PAREG[15] $ B1_PASTEP[15] $ M11_cout[8];

--M11L39 is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[9]~343 at LC5_D16
--operation mode is arithmetic

M11L39 = B1_PAREG[15] $ B1_PASTEP[15] $ M11_cout[8];

--M11_cout[9] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[9] at LC5_D16
--operation mode is arithmetic

M11_cout[9] = CARRY(B1_PAREG[15] & (B1_PASTEP[15] # M11_cout[8]) # !B1_PAREG[15] & B1_PASTEP[15] & M11_cout[8]);


--M14_cs_buffer[10] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[10] at LC6_D32
--operation mode is arithmetic

M14_cs_buffer[10] = B1_PASTEP[16] $ M14_cout[9];

--M14L42 is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[10]~229 at LC6_D32
--operation mode is arithmetic

M14L42 = B1_PASTEP[16] $ M14_cout[9];

--M14_cout[10] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[10] at LC6_D32
--operation mode is arithmetic

M14_cout[10] = CARRY(B1_PASTEP[16] & M14_cout[9]);


--M17_cs_buffer[10] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[10] at LC6_D31
--operation mode is arithmetic

M17_cs_buffer[10] = B1_PASTEP[16] $ M17_cout[9];

--M17L39 is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[10]~340 at LC6_D31
--operation mode is arithmetic

M17L39 = B1_PASTEP[16] $ M17_cout[9];

--M17_cout[10] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[10] at LC6_D31
--operation mode is arithmetic

M17_cout[10] = CARRY(B1_PASTEP[16] # M17_cout[9]);


--B1_PASTEP[15] is PhaseAcc:inst|PASTEP[15] at LC5_D28
--operation mode is normal

B1_PASTEP[15]_lut_out = FreDec & (M14_cs_buffer[9]) # !FreDec & !M17_cs_buffer[9];
B1_PASTEP[15] = DFFEA(B1_PASTEP[15]_lut_out, B1_EVENTCHECK, GLOBAL(RST), , , , );

--B1L64Q is PhaseAcc:inst|PASTEP[15]~380 at LC5_D28
--operation mode is normal

B1L64Q = B1_PASTEP[15];


--B1_PAREG[15] is PhaseAcc:inst|PAREG[15] at LC1_D5
--operation mode is normal

B1_PAREG[15]_lut_out = M11_cs_buffer[9];
B1_PAREG[15] = DFFEA(B1_PAREG[15]_lut_out, !GLOBAL(B1_FP2), GLOBAL(RST), , , , );

--B1L25Q is PhaseAcc:inst|PAREG[15]~78 at LC1_D5
--operation mode is normal

B1L25Q = B1_PAREG[15];


--M11_cs_buffer[8] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[8] at LC4_D16
--operation mode is arithmetic

M11_cs_buffer[8] = B1_PAREG[14] $ B1_PASTEP[14] $ M11_cout[7];

--M11L37 is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]~344 at LC4_D16
--operation mode is arithmetic

M11L37 = B1_PAREG[14] $ B1_PASTEP[14] $ M11_cout[7];

--M11_cout[8] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[8] at LC4_D16
--operation mode is arithmetic

M11_cout[8] = CARRY(B1_PAREG[14] & (B1_PASTEP[14] # M11_cout[7]) # !B1_PAREG[14] & B1_PASTEP[14] & M11_cout[7]);


--M14_cs_buffer[9] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[9] at LC5_D32
--operation mode is arithmetic

M14_cs_buffer[9] = B1_PASTEP[15] $ M14_cout[8];

--M14L40 is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[9]~230 at LC5_D32
--operation mode is arithmetic

M14L40 = B1_PASTEP[15] $ M14_cout[8];

--M14_cout[9] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[9] at LC5_D32
--operation mode is arithmetic

M14_cout[9] = CARRY(B1_PASTEP[15] & M14_cout[8]);


--M17_cs_buffer[9] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[9] at LC5_D31
--operation mode is arithmetic

M17_cs_buffer[9] = B1_PASTEP[15] $ M17_cout[8];

--M17L37 is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[9]~341 at LC5_D31
--operation mode is arithmetic

M17L37 = B1_PASTEP[15] $ M17_cout[8];

--M17_cout[9] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[9] at LC5_D31
--operation mode is arithmetic

M17_cout[9] = CARRY(B1_PASTEP[15] # M17_cout[8]);


--B1_PASTEP[14] is PhaseAcc:inst|PASTEP[14] at LC4_D28
--operation mode is normal

B1_PASTEP[14]_lut_out = FreDec & (M14_cs_buffer[8]) # !FreDec & !M17_cs_buffer[8];
B1_PASTEP[14] = DFFEA(B1_PASTEP[14]_lut_out, B1_EVENTCHECK, GLOBAL(RST), , , , );

--B1L62Q is PhaseAcc:inst|PASTEP[14]~381 at LC4_D28
--operation mode is normal

B1L62Q = B1_PASTEP[14];


--B1_PAREG[14] is PhaseAcc:inst|PAREG[14] at LC1_D6
--operation mode is normal

B1_PAREG[14]_lut_out = M11_cs_buffer[8];
B1_PAREG[14] = DFFEA(B1_PAREG[14]_lut_out, !GLOBAL(B1_FP2), GLOBAL(RST), , , , );

--B1L23Q is PhaseAcc:inst|PAREG[14]~79 at LC1_D6
--operation mode is normal

B1L23Q = B1_PAREG[14];


--M11_cs_buffer[7] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] at LC3_D16
--operation mode is arithmetic

M11_cs_buffer[7] = B1_PAREG[13] $ B1_PASTEP[13] $ M11_cout[6];

--M11L35 is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~345 at LC3_D16
--operation mode is arithmetic

M11L35 = B1_PAREG[13] $ B1_PASTEP[13] $ M11_cout[6];

--M11_cout[7] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[7] at LC3_D16
--operation mode is arithmetic

M11_cout[7] = CARRY(B1_PAREG[13] & (B1_PASTEP[13] # M11_cout[6]) # !B1_PAREG[13] & B1_PASTEP[13] & M11_cout[6]);


--M14_cs_buffer[8] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[8] at LC4_D32
--operation mode is arithmetic

M14_cs_buffer[8] = B1_PASTEP[14] $ M14_cout[7];

--M14L38 is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]~231 at LC4_D32
--operation mode is arithmetic

M14L38 = B1_PASTEP[14] $ M14_cout[7];

--M14_cout[8] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[8] at LC4_D32
--operation mode is arithmetic

M14_cout[8] = CARRY(B1_PASTEP[14] & M14_cout[7]);


--M17_cs_buffer[8] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[8] at LC4_D31
--operation mode is arithmetic

M17_cs_buffer[8] = B1_PASTEP[14] $ M17_cout[7];

--M17L35 is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]~342 at LC4_D31
--operation mode is arithmetic

M17L35 = B1_PASTEP[14] $ M17_cout[7];

--M17_cout[8] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[8] at LC4_D31
--operation mode is arithmetic

M17_cout[8] = CARRY(B1_PASTEP[14] # M17_cout[7]);


--B1_PASTEP[13] is PhaseAcc:inst|PASTEP[13] at LC3_D28
--operation mode is normal

B1_PASTEP[13]_lut_out = FreDec & (M14_cs_buffer[7]) # !FreDec & !M17_cs_buffer[7];
B1_PASTEP[13] = DFFEA(B1_PASTEP[13]_lut_out, B1_EVENTCHECK, GLOBAL(RST), , , , );

--B1L60Q is PhaseAcc:inst|PASTEP[13]~382 at LC3_D28
--operation mode is normal

B1L60Q = B1_PASTEP[13];


--B1_PAREG[13] is PhaseAcc:inst|PAREG[13] at LC1_D4
--operation mode is normal

B1_PAREG[13]_lut_out = M11_cs_buffer[7];
B1_PAREG[13] = DFFEA(B1_PAREG[13]_lut_out, !GLOBAL(B1_FP2), GLOBAL(RST), , , , );

--B1L21Q is PhaseAcc:inst|PAREG[13]~80 at LC1_D4
--operation mode is normal

B1L21Q = B1_PAREG[13];


--M11_cs_buffer[6] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] at LC2_D16
--operation mode is arithmetic

M11_cs_buffer[6] = B1_PAREG[12] $ B1_PASTEP[12] $ M11_cout[5];

--M11L33 is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~346 at LC2_D16
--operation mode is arithmetic

M11L33 = B1_PAREG[12] $ B1_PASTEP[12] $ M11_cout[5];

--M11_cout[6] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[6] at LC2_D16
--operation mode is arithmetic

M11_cout[6] = CARRY(B1_PAREG[12] & (B1_PASTEP[12] # M11_cout[5]) # !B1_PAREG[12] & B1_PASTEP[12] & M11_cout[5]);


--M14_cs_buffer[7] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] at LC3_D32
--operation mode is arithmetic

M14_cs_buffer[7] = B1_PASTEP[13] $ M14_cout[6];

--M14L36 is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~232 at LC3_D32
--operation mode is arithmetic

M14L36 = B1_PASTEP[13] $ M14_cout[6];

--M14_cout[7] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[7] at LC3_D32
--operation mode is arithmetic

M14_cout[7] = CARRY(B1_PASTEP[13] & M14_cout[6]);


--M17_cs_buffer[7] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] at LC3_D31
--operation mode is arithmetic

M17_cs_buffer[7] = B1_PASTEP[13] $ M17_cout[6];

--M17L33 is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~343 at LC3_D31
--operation mode is arithmetic

M17L33 = B1_PASTEP[1