dds.fit.eqn

利用FPGA的资源实现任意波形的产生

G1L24 = P2_q[4] & PathSel[1];


--P4_q[3] is lpm_rom_sin:inst1|lpm_rom:lpm_rom_component|altrom:srom|q[3] at EC4_D
P4_q[3]_clock_0 = GLOBAL(B1_FP2);
P4_q[3]_clock_1 = GLOBAL(B1_FP2);
P4_q[3]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P4_q[3]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P4_q[3] = MEMORY_SEGMENT(, , P4_q[3]_clock_0, P4_q[3]_clock_1, , , , , P4_q[3]_write_address, P4_q[3]_read_address);


--G1_sinreg[3] is PathSel:inst5|sinreg[3] at LC7_B35
--operation mode is normal

G1_sinreg[3] = P4_q[3] & PathSel[0];

--G1L48 is PathSel:inst5|sinreg[3]~75 at LC7_B35
--operation mode is normal

G1L48 = P4_q[3] & PathSel[0];


--P2_q[3] is lpm_rom_juchi:inst2|lpm_rom:lpm_rom_component|altrom:srom|q[3] at EC14_D
P2_q[3]_clock_0 = GLOBAL(B1_FP2);
P2_q[3]_clock_1 = GLOBAL(B1_FP2);
P2_q[3]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P2_q[3]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P2_q[3] = MEMORY_SEGMENT(, , P2_q[3]_clock_0, P2_q[3]_clock_1, , , , , P2_q[3]_write_address, P2_q[3]_read_address);


--G1_juchireg[3] is PathSel:inst5|juchireg[3] at LC8_B35
--operation mode is normal

G1_juchireg[3] = P2_q[3] & PathSel[1];

--G1L22 is PathSel:inst5|juchireg[3]~60 at LC8_B35
--operation mode is normal

G1L22 = P2_q[3] & PathSel[1];


--P4_q[2] is lpm_rom_sin:inst1|lpm_rom:lpm_rom_component|altrom:srom|q[2] at EC1_D
P4_q[2]_clock_0 = GLOBAL(B1_FP2);
P4_q[2]_clock_1 = GLOBAL(B1_FP2);
P4_q[2]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P4_q[2]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P4_q[2] = MEMORY_SEGMENT(, , P4_q[2]_clock_0, P4_q[2]_clock_1, , , , , P4_q[2]_write_address, P4_q[2]_read_address);


--G1_sinreg[2] is PathSel:inst5|sinreg[2] at LC6_B31
--operation mode is normal

G1_sinreg[2] = P4_q[2] & PathSel[0];

--G1L46 is PathSel:inst5|sinreg[2]~76 at LC6_B31
--operation mode is normal

G1L46 = P4_q[2] & PathSel[0];


--P2_q[2] is lpm_rom_juchi:inst2|lpm_rom:lpm_rom_component|altrom:srom|q[2] at EC9_D
P2_q[2]_clock_0 = GLOBAL(B1_FP2);
P2_q[2]_clock_1 = GLOBAL(B1_FP2);
P2_q[2]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P2_q[2]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P2_q[2] = MEMORY_SEGMENT(, , P2_q[2]_clock_0, P2_q[2]_clock_1, , , , , P2_q[2]_write_address, P2_q[2]_read_address);


--G1_juchireg[2] is PathSel:inst5|juchireg[2] at LC7_B31
--operation mode is normal

G1_juchireg[2] = P2_q[2] & PathSel[1];

--G1L20 is PathSel:inst5|juchireg[2]~61 at LC7_B31
--operation mode is normal

G1L20 = P2_q[2] & PathSel[1];


--P4_q[1] is lpm_rom_sin:inst1|lpm_rom:lpm_rom_component|altrom:srom|q[1] at EC6_D
P4_q[1]_clock_0 = GLOBAL(B1_FP2);
P4_q[1]_clock_1 = GLOBAL(B1_FP2);
P4_q[1]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P4_q[1]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P4_q[1] = MEMORY_SEGMENT(, , P4_q[1]_clock_0, P4_q[1]_clock_1, , , , , P4_q[1]_write_address, P4_q[1]_read_address);


--G1_sinreg[1] is PathSel:inst5|sinreg[1] at LC3_D20
--operation mode is normal

G1_sinreg[1] = P4_q[1] & PathSel[0];

--G1L44 is PathSel:inst5|sinreg[1]~77 at LC3_D20
--operation mode is normal

G1L44 = P4_q[1] & PathSel[0];


--P2_q[1] is lpm_rom_juchi:inst2|lpm_rom:lpm_rom_component|altrom:srom|q[1] at EC11_D
P2_q[1]_clock_0 = GLOBAL(B1_FP2);
P2_q[1]_clock_1 = GLOBAL(B1_FP2);
P2_q[1]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P2_q[1]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P2_q[1] = MEMORY_SEGMENT(, , P2_q[1]_clock_0, P2_q[1]_clock_1, , , , , P2_q[1]_write_address, P2_q[1]_read_address);


--G1_juchireg[1] is PathSel:inst5|juchireg[1] at LC5_D20
--operation mode is normal

G1_juchireg[1] = P2_q[1] & PathSel[1];

--G1L18 is PathSel:inst5|juchireg[1]~62 at LC5_D20
--operation mode is normal

G1L18 = P2_q[1] & PathSel[1];


--P2_q[0] is lpm_rom_juchi:inst2|lpm_rom:lpm_rom_component|altrom:srom|q[0] at EC3_D
P2_q[0]_clock_0 = GLOBAL(B1_FP2);
P2_q[0]_clock_1 = GLOBAL(B1_FP2);
P2_q[0]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P2_q[0]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P2_q[0] = MEMORY_SEGMENT(, , P2_q[0]_clock_0, P2_q[0]_clock_1, , , , , P2_q[0]_write_address, P2_q[0]_read_address);


--G1_juchireg[0] is PathSel:inst5|juchireg[0] at LC6_D20
--operation mode is normal

G1_juchireg[0] = P2_q[0] & PathSel[1];

--G1L16 is PathSel:inst5|juchireg[0]~63 at LC6_D20
--operation mode is normal

G1L16 = P2_q[0] & PathSel[1];


--P4_q[0] is lpm_rom_sin:inst1|lpm_rom:lpm_rom_component|altrom:srom|q[0] at EC10_D
P4_q[0]_clock_0 = GLOBAL(B1_FP2);
P4_q[0]_clock_1 = GLOBAL(B1_FP2);
P4_q[0]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P4_q[0]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P4_q[0] = MEMORY_SEGMENT(, , P4_q[0]_clock_0, P4_q[0]_clock_1, , , , , P4_q[0]_write_address, P4_q[0]_read_address);


--G1_sinreg[0] is PathSel:inst5|sinreg[0] at LC7_D20
--operation mode is normal

G1_sinreg[0] = P4_q[0] & PathSel[0];

--G1L42 is PathSel:inst5|sinreg[0]~78 at LC7_D20
--operation mode is normal

G1L42 = P4_q[0] & PathSel[0];


--M14_cs_buffer[12] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[12] at LC8_D32
--operation mode is arithmetic

M14_cs_buffer[12] = B1_PASTEP[18] $ !M14_cout[11];

--M14L46 is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[12]~223 at LC8_D32
--operation mode is arithmetic

M14L46 = B1_PASTEP[18] $ !M14_cout[11];

--M14_cout[12] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[12] at LC8_D32
--operation mode is arithmetic

M14_cout[12] = CARRY(!B1_PASTEP[18] & M14_cout[11]);


--M17_cs_buffer[12] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[12] at LC8_D31
--operation mode is arithmetic

M17_cs_buffer[12] = B1_PASTEP[18] $ !M17_cout[11];

--M17L43 is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[12]~334 at LC8_D31
--operation mode is arithmetic

M17L43 = B1_PASTEP[18] $ !M17_cout[11];

--M17_cout[12] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[12] at LC8_D31
--operation mode is arithmetic

M17_cout[12] = CARRY(M17_cout[11] # !B1_PASTEP[18]);


--M14_cs_buffer[13] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[13] at LC1_D34
--operation mode is arithmetic

M14_cs_buffer[13] = B1_PASTEP[19] $ M14_cout[12];

--M14L48 is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[13]~224 at LC1_D34
--operation mode is arithmetic

M14L48 = B1_PASTEP[19] $ M14_cout[12];

--M14_cout[13] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[13] at LC1_D34
--operation mode is arithmetic

M14_cout[13] = CARRY(B1_PASTEP[19] & M14_cout[12]);


--M17_cs_buffer[13] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[13] at LC1_D33
--operation mode is arithmetic

M17_cs_buffer[13] = B1_PASTEP[19] $ M17_cout[12];

--M17L45 is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[13]~335 at LC1_D33
--operation mode is arithmetic

M17L45 = B1_PASTEP[19] $ M17_cout[12];

--M17_cout[13] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[13] at LC1_D33
--operation mode is arithmetic

M17_cout[13] = CARRY(B1_PASTEP[19] # M17_cout[12]);


--M14_cs_buffer[14] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[14] at LC2_D34
--operation mode is arithmetic

M14_cs_buffer[14] = B1_PASTEP[20] $ M14_cout[13];

--M14L50 is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[14]~225 at LC2_D34
--operation mode is arithmetic

M14L50 = B1_PASTEP[20] $ M14_cout[13];

--M14_cout[14] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[14] at LC2_D34
--operation mode is arithmetic

M14_cout[14] = CARRY(B1_PASTEP[20] & M14_cout[13]);


--M17_cs_buffer[14] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[14] at LC2_D33
--operation mode is arithmetic

M17_cs_buffer[14] = B1_PASTEP[20] $ M17_cout[13];

--M17L47 is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[14]~336 at LC2_D33
--operation mode is arithmetic

M17L47 = B1_PASTEP[20] $ M17_cout[13];

--M17_cout[14] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[14] at LC2_D33
--operation mode is arithmetic

M17_cout[14] = CARRY(B1_PASTEP[20] # M17_cout[13]);


--M14_cs_buffer[15] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[15] at LC3_D34
--operation mode is arithmetic

M14_cs_buffer[15] = B1_PASTEP[21] $ M14_cout[14];

--M14L52 is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[15]~226 at LC3_D34
--operation mode is arithmetic

M14L52 = B1_PASTEP[21] $ M14_cout[14];

--M14_cout[15] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[15] at LC3_D34
--operation mode is arithmetic

M14_cout[15] = CARRY(B1_PASTEP[21] & M14_cout[14]);


--M17_cs_buffer[15] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[15] at LC3_D33
--operation mode is arithmetic

M17_cs_buffer[15] = B1_PASTEP[21] $ M17_cout[14];

--M17L49 is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[15]~337 at LC3_D33
--operation mode is arithmetic

M17L49 = B1_PASTEP[21] $ M17_cout[14];

--M17_cout[15] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[15] at LC3_D33
--operation mode is arithmetic

M17_cout[15] = CARRY(B1_PASTEP[21] # M17_cout[14]);


--M14_cs_buffer[16] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[16] at LC4_D34
--operation mode is arithmetic

M14_cs_buffer[16] = B1_PASTEP[22] $ M14_cout[15];

--M14L54 is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cs_buffer[16]~227 at LC4_D34
--operation mode is arithmetic

M14L54 = B1_PASTEP[22] $ M14_cout[15];

--M14_cout[16] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[16] at LC4_D34
--operation mode is arithmetic

M14_cout[16] = CARRY(B1_PASTEP[22] & M14_cout[15]);


--M17_cs_buffer[16] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[16] at LC4_D33
--operation mode is arithmetic

M17_cs_buffer[16] = B1_PASTEP[22] $ M17_cout[15];

--M17L51 is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cs_buffer[16]~338 at LC4_D33
--operation mode is arithmetic

M17L51 = B1_PASTEP[22] $ M17_cout[15];

--M17_cout[16] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|a_csnbuffer:result_node|cout[16] at LC4_D33
--operation mode is arithmetic

M17_cout[16] = CARRY(B1_PASTEP[22] # M17_cout[15]);


--K5_unreg_res_node[17] is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|unreg_res_node[17] at LC5_D34
--operation mode is normal

K5_unreg_res_node[17] = M14_cout[16] $ B1_PASTEP[23];

--K5L3 is PhaseAcc:inst|lpm_add_sub:add_rtl_4|addcore:adder|unreg_res_node[17]~36 at LC5_D34
--operation mode is normal

K5L3 = M14_cout[16] $ B1_PASTEP[23];


--K6_unreg_res_node[17] is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|unreg_res_node[17] at LC5_D33
--operation mode is normal

K6_unreg_res_node[17] = M17_cout[16] $ B1_PASTEP[23];

--K6L3 is PhaseAcc:inst|lpm_add_sub:add_rtl_5|addcore:adder|unreg_res_node[17]~35 at LC5_D33
--operation mode is normal

K6L3 = M17_cout[16] $ B1_PASTEP[23];


--B1_PASTEP[17] is PhaseAcc:inst|PASTEP[17] at LC7_D28
--operation mode is normal

B1_PASTEP[17]_lut_out = FreDec & (M14_cs_buffer[11]) # !FreDec & !M17_cs_buffer[11];
B1_PASTEP[17] = DFFEA(B1_PASTEP[17]_lut_out, B1_EVENTCHECK, GLOBAL(RST), , , , );

--B1L68Q is PhaseAcc:inst|PASTEP[17]~378 at LC7_D28
--operation mode is normal