dds.fit.eqn

利用FPGA的资源实现任意波形的产生

--G1_sanjiaoreg[1] is PathSel:inst5|sanjiaoreg[1] at LC6_B32
--operation mode is normal

G1_sanjiaoreg[1] = P3_q[1] & PathSel[2];

--G1L31 is PathSel:inst5|sanjiaoreg[1]~62 at LC6_B32
--operation mode is normal

G1L31 = P3_q[1] & PathSel[2];


--P3_q[0] is lpm_rom_sanjiao:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[0] at EC13_B
P3_q[0]_clock_0 = GLOBAL(B1_FP2);
P3_q[0]_clock_1 = GLOBAL(B1_FP2);
P3_q[0]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P3_q[0]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P3_q[0] = MEMORY_SEGMENT(, , P3_q[0]_clock_0, P3_q[0]_clock_1, , , , , P3_q[0]_write_address, P3_q[0]_read_address);


--G1_sanjiaoreg[0] is PathSel:inst5|sanjiaoreg[0] at LC7_B32
--operation mode is normal

G1_sanjiaoreg[0] = P3_q[0] & PathSel[2];

--G1L29 is PathSel:inst5|sanjiaoreg[0]~63 at LC7_B32
--operation mode is normal

G1L29 = P3_q[0] & PathSel[2];


--M2L21 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~103 at LC2_B19
--operation mode is normal

M2L21 = M2L18 $ G1_juchireg[5] $ G1_sinreg[5];

--M2L23 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~147 at LC2_B19
--operation mode is normal

M2L23 = M2L18 $ G1_juchireg[5] $ G1_sinreg[5];


--M2L22 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~107 at LC1_B19
--operation mode is normal

M2L22 = M2L18 & (G1_juchireg[5] # G1_sinreg[5]) # !M2L18 & G1_juchireg[5] & G1_sinreg[5];

--M2L24 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~148 at LC1_B19
--operation mode is normal

M2L24 = M2L18 & (G1_juchireg[5] # G1_sinreg[5]) # !M2L18 & G1_juchireg[5] & G1_sinreg[5];


--B1_PASTEP[23] is PhaseAcc:inst|PASTEP[23] at LC6_D34
--operation mode is normal

B1_PASTEP[23]_lut_out = FreDec & (K5_unreg_res_node[17]) # !FreDec & !K6_unreg_res_node[17];
B1_PASTEP[23] = DFFEA(B1_PASTEP[23]_lut_out, B1_EVENTCHECK, GLOBAL(RST), , , , );

--B1L80Q is PhaseAcc:inst|PASTEP[23]~372 at LC6_D34
--operation mode is normal

B1L80Q = B1_PASTEP[23];


--K4_unreg_res_node[17] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|unreg_res_node[17] at LC5_D18
--operation mode is normal

K4_unreg_res_node[17] = B1_PAREG[23] $ M11_cout[16] $ B1_PASTEP[23];

--K4L3 is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|unreg_res_node[17]~53 at LC5_D18
--operation mode is normal

K4L3 = B1_PAREG[23] $ M11_cout[16] $ B1_PASTEP[23];


--M2L17 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~111 at LC3_B35
--operation mode is normal

M2L17 = M2L14 $ G1_juchireg[4] $ G1_sinreg[4];

--M2L19 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~149 at LC3_B35
--operation mode is normal

M2L19 = M2L14 $ G1_juchireg[4] $ G1_sinreg[4];


--M2L18 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~115 at LC2_B35
--operation mode is normal

M2L18 = M2L14 & (G1_juchireg[4] # G1_sinreg[4]) # !M2L14 & G1_juchireg[4] & G1_sinreg[4];

--M2L20 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~150 at LC2_B35
--operation mode is normal

M2L20 = M2L14 & (G1_juchireg[4] # G1_sinreg[4]) # !M2L14 & G1_juchireg[4] & G1_sinreg[4];


--M2L13 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~119 at LC1_B35
--operation mode is normal

M2L13 = M2L10 $ G1_juchireg[3] $ G1_sinreg[3];

--M2L15 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~151 at LC1_B35
--operation mode is normal

M2L15 = M2L10 $ G1_juchireg[3] $ G1_sinreg[3];


--M2L14 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~123 at LC4_B35
--operation mode is normal

M2L14 = M2L10 & (G1_juchireg[3] # G1_sinreg[3]) # !M2L10 & G1_juchireg[3] & G1_sinreg[3];

--M2L16 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~152 at LC4_B35
--operation mode is normal

M2L16 = M2L10 & (G1_juchireg[3] # G1_sinreg[3]) # !M2L10 & G1_juchireg[3] & G1_sinreg[3];


--M2L9 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~127 at LC5_B31
--operation mode is normal

M2L9 = M2L6 $ G1_juchireg[2] $ G1_sinreg[2];

--M2L11 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~153 at LC5_B31
--operation mode is normal

M2L11 = M2L6 $ G1_juchireg[2] $ G1_sinreg[2];


--M2L10 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~131 at LC2_B31
--operation mode is normal

M2L10 = M2L6 & (G1_juchireg[2] # G1_sinreg[2]) # !M2L6 & G1_juchireg[2] & G1_sinreg[2];

--M2L12 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~154 at LC2_B31
--operation mode is normal

M2L12 = M2L6 & (G1_juchireg[2] # G1_sinreg[2]) # !M2L6 & G1_juchireg[2] & G1_sinreg[2];


--M2L5 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~135 at LC1_D20
--operation mode is normal

M2L5 = M2L2 $ G1_juchireg[1] $ G1_sinreg[1];

--M2L7 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~155 at LC1_D20
--operation mode is normal

M2L7 = M2L2 $ G1_juchireg[1] $ G1_sinreg[1];


--M2L6 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~139 at LC4_D20
--operation mode is normal

M2L6 = M2L2 & (G1_juchireg[1] # G1_sinreg[1]) # !M2L2 & G1_juchireg[1] & G1_sinreg[1];

--M2L8 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~156 at LC4_D20
--operation mode is normal

M2L8 = M2L2 & (G1_juchireg[1] # G1_sinreg[1]) # !M2L2 & G1_juchireg[1] & G1_sinreg[1];


--M2L1 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~142 at LC8_D20
--operation mode is normal

M2L1 = G1_sinreg[0] $ G1_juchireg[0];

--M2L3 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~157 at LC8_D20
--operation mode is normal

M2L3 = G1_sinreg[0] $ G1_juchireg[0];


--M2L2 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~145 at LC2_D20
--operation mode is normal

M2L2 = G1_sinreg[0] & G1_juchireg[0];

--M2L4 is PathSel:inst5|lpm_add_sub:add_rtl_0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~158 at LC2_D20
--operation mode is normal

M2L4 = G1_sinreg[0] & G1_juchireg[0];


--P4_q[5] is lpm_rom_sin:inst1|lpm_rom:lpm_rom_component|altrom:srom|q[5] at EC2_B
P4_q[5]_clock_0 = GLOBAL(B1_FP2);
P4_q[5]_clock_1 = GLOBAL(B1_FP2);
P4_q[5]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P4_q[5]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P4_q[5] = MEMORY_SEGMENT(, , P4_q[5]_clock_0, P4_q[5]_clock_1, , , , , P4_q[5]_write_address, P4_q[5]_read_address);


--G1_sinreg[5] is PathSel:inst5|sinreg[5] at LC3_B19
--operation mode is normal

G1_sinreg[5] = PathSel[0] & P4_q[5];

--G1L52 is PathSel:inst5|sinreg[5]~73 at LC3_B19
--operation mode is normal

G1L52 = PathSel[0] & P4_q[5];


--P2_q[5] is lpm_rom_juchi:inst2|lpm_rom:lpm_rom_component|altrom:srom|q[5] at EC10_B
P2_q[5]_clock_0 = GLOBAL(B1_FP2);
P2_q[5]_clock_1 = GLOBAL(B1_FP2);
P2_q[5]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P2_q[5]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P2_q[5] = MEMORY_SEGMENT(, , P2_q[5]_clock_0, P2_q[5]_clock_1, , , , , P2_q[5]_write_address, P2_q[5]_read_address);


--G1_juchireg[5] is PathSel:inst5|juchireg[5] at LC4_B19
--operation mode is normal

G1_juchireg[5] = PathSel[1] & P2_q[5];

--G1L26 is PathSel:inst5|juchireg[5]~58 at LC4_B19
--operation mode is normal

G1L26 = PathSel[1] & P2_q[5];


--B1_PASTEP[18] is PhaseAcc:inst|PASTEP[18] at LC8_D28
--operation mode is normal

B1_PASTEP[18]_lut_out = FreDec & (!M14_cs_buffer[12]) # !FreDec & M17_cs_buffer[12];
B1_PASTEP[18] = DFFEA(B1_PASTEP[18]_lut_out, B1_EVENTCHECK, GLOBAL(RST), , , , );

--B1L70Q is PhaseAcc:inst|PASTEP[18]~373 at LC8_D28
--operation mode is normal

B1L70Q = B1_PASTEP[18];


--M11_cs_buffer[11] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[11] at LC7_D16
--operation mode is arithmetic

M11_cs_buffer[11] = B1_PAREG[17] $ B1_PASTEP[17] $ M11_cout[10];

--M11L43 is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[11]~341 at LC7_D16
--operation mode is arithmetic

M11L43 = B1_PAREG[17] $ B1_PASTEP[17] $ M11_cout[10];

--M11_cout[11] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[11] at LC7_D16
--operation mode is arithmetic

M11_cout[11] = CARRY(B1_PAREG[17] & (B1_PASTEP[17] # M11_cout[10]) # !B1_PAREG[17] & B1_PASTEP[17] & M11_cout[10]);


--B1_PASTEP[19] is PhaseAcc:inst|PASTEP[19] at LC6_D33
--operation mode is normal

B1_PASTEP[19]_lut_out = FreDec & (M14_cs_buffer[13]) # !FreDec & !M17_cs_buffer[13];
B1_PASTEP[19] = DFFEA(B1_PASTEP[19]_lut_out, B1_EVENTCHECK, GLOBAL(RST), , , , );

--B1L72Q is PhaseAcc:inst|PASTEP[19]~374 at LC6_D33
--operation mode is normal

B1L72Q = B1_PASTEP[19];


--B1_PASTEP[20] is PhaseAcc:inst|PASTEP[20] at LC8_D33
--operation mode is normal

B1_PASTEP[20]_lut_out = FreDec & (M14_cs_buffer[14]) # !FreDec & !M17_cs_buffer[14];
B1_PASTEP[20] = DFFEA(B1_PASTEP[20]_lut_out, B1_EVENTCHECK, GLOBAL(RST), , , , );

--B1L74Q is PhaseAcc:inst|PASTEP[20]~375 at LC8_D33
--operation mode is normal

B1L74Q = B1_PASTEP[20];


--B1_PASTEP[21] is PhaseAcc:inst|PASTEP[21] at LC7_D34
--operation mode is normal

B1_PASTEP[21]_lut_out = FreDec & (M14_cs_buffer[15]) # !FreDec & !M17_cs_buffer[15];
B1_PASTEP[21] = DFFEA(B1_PASTEP[21]_lut_out, B1_EVENTCHECK, GLOBAL(RST), , , , );

--B1L76Q is PhaseAcc:inst|PASTEP[21]~376 at LC7_D34
--operation mode is normal

B1L76Q = B1_PASTEP[21];


--B1_PASTEP[22] is PhaseAcc:inst|PASTEP[22] at LC8_D34
--operation mode is normal

B1_PASTEP[22]_lut_out = FreDec & (M14_cs_buffer[16]) # !FreDec & !M17_cs_buffer[16];
B1_PASTEP[22] = DFFEA(B1_PASTEP[22]_lut_out, B1_EVENTCHECK, GLOBAL(RST), , , , );

--B1L78Q is PhaseAcc:inst|PASTEP[22]~377 at LC8_D34
--operation mode is normal

B1L78Q = B1_PASTEP[22];


--B1_EVENTCHECK is PhaseAcc:inst|EVENTCHECK at LC1_D29
--operation mode is normal

B1_EVENTCHECK = !FreDec # !FreInc;

--B1L2 is PhaseAcc:inst|EVENTCHECK~7 at LC1_D29
--operation mode is normal

B1L2 = !FreDec # !FreInc;


--P4_q[4] is lpm_rom_sin:inst1|lpm_rom:lpm_rom_component|altrom:srom|q[4] at EC2_D
P4_q[4]_clock_0 = GLOBAL(B1_FP2);
P4_q[4]_clock_1 = GLOBAL(B1_FP2);
P4_q[4]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P4_q[4]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P4_q[4] = MEMORY_SEGMENT(, , P4_q[4]_clock_0, P4_q[4]_clock_1, , , , , P4_q[4]_write_address, P4_q[4]_read_address);


--G1_sinreg[4] is PathSel:inst5|sinreg[4] at LC5_B35
--operation mode is normal

G1_sinreg[4] = P4_q[4] & PathSel[0];

--G1L50 is PathSel:inst5|sinreg[4]~74 at LC5_B35
--operation mode is normal

G1L50 = P4_q[4] & PathSel[0];


--P2_q[4] is lpm_rom_juchi:inst2|lpm_rom:lpm_rom_component|altrom:srom|q[4] at EC16_D
P2_q[4]_clock_0 = GLOBAL(B1_FP2);
P2_q[4]_clock_1 = GLOBAL(B1_FP2);
P2_q[4]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P2_q[4]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P2_q[4] = MEMORY_SEGMENT(, , P2_q[4]_clock_0, P2_q[4]_clock_1, , , , , P2_q[4]_write_address, P2_q[4]_read_address);


--G1_juchireg[4] is PathSel:inst5|juchireg[4] at LC6_B35
--operation mode is normal

G1_juchireg[4] = P2_q[4] & PathSel[1];

--G1L24 is PathSel:inst5|juchireg[4]~59 at LC6_B35
--operation mode is normal