dds.fit.eqn

利用FPGA的资源实现任意波形的产生

--B1_PAREG[18] is PhaseAcc:inst|PAREG[18] at LC1_D17
--operation mode is normal

B1_PAREG[18]_lut_out = M11_cs_buffer[12];
B1_PAREG[18] = DFFEA(B1_PAREG[18]_lut_out, !GLOBAL(B1_FP2), GLOBAL(RST), , , , );

--B1L31Q is PhaseAcc:inst|PAREG[18]~70 at LC1_D17
--operation mode is normal

B1L31Q = B1_PAREG[18];


--B1_PAREG[19] is PhaseAcc:inst|PAREG[19] at LC8_D18
--operation mode is normal

B1_PAREG[19]_lut_out = M11_cs_buffer[13];
B1_PAREG[19] = DFFEA(B1_PAREG[19]_lut_out, !GLOBAL(B1_FP2), GLOBAL(RST), , , , );

--B1L33Q is PhaseAcc:inst|PAREG[19]~71 at LC8_D18
--operation mode is normal

B1L33Q = B1_PAREG[19];


--B1_PAREG[20] is PhaseAcc:inst|PAREG[20] at LC7_D18
--operation mode is normal

B1_PAREG[20]_lut_out = M11_cs_buffer[14];
B1_PAREG[20] = DFFEA(B1_PAREG[20]_lut_out, !GLOBAL(B1_FP2), GLOBAL(RST), , , , );

--B1L35Q is PhaseAcc:inst|PAREG[20]~72 at LC7_D18
--operation mode is normal

B1L35Q = B1_PAREG[20];


--B1_PAREG[21] is PhaseAcc:inst|PAREG[21] at LC1_D11
--operation mode is normal

B1_PAREG[21]_lut_out = M11_cs_buffer[15];
B1_PAREG[21] = DFFEA(B1_PAREG[21]_lut_out, !GLOBAL(B1_FP2), GLOBAL(RST), , , , );

--B1L37Q is PhaseAcc:inst|PAREG[21]~73 at LC1_D11
--operation mode is normal

B1L37Q = B1_PAREG[21];


--B1_PAREG[22] is PhaseAcc:inst|PAREG[22] at LC1_D13
--operation mode is normal

B1_PAREG[22]_lut_out = M11_cs_buffer[16];
B1_PAREG[22] = DFFEA(B1_PAREG[22]_lut_out, !GLOBAL(B1_FP2), GLOBAL(RST), , , , );

--B1L39Q is PhaseAcc:inst|PAREG[22]~74 at LC1_D13
--operation mode is normal

B1L39Q = B1_PAREG[22];


--B1_PAREG[23] is PhaseAcc:inst|PAREG[23] at LC6_D18
--operation mode is normal

B1_PAREG[23]_lut_out = K4_unreg_res_node[17];
B1_PAREG[23] = DFFEA(B1_PAREG[23]_lut_out, !GLOBAL(B1_FP2), GLOBAL(RST), , , , );

--B1L41Q is PhaseAcc:inst|PAREG[23]~75 at LC6_D18
--operation mode is normal

B1L41Q = B1_PAREG[23];


--M5L17 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~139 at LC1_B26
--operation mode is normal

M5L17 = M5L14 $ G1_sanjiaoreg[4] $ M2L17;

--M5L19 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~179 at LC1_B26
--operation mode is normal

M5L19 = M5L14 $ G1_sanjiaoreg[4] $ M2L17;


--M5L18 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~143 at LC4_B26
--operation mode is normal

M5L18 = M5L14 & (G1_sanjiaoreg[4] # M2L17) # !M5L14 & G1_sanjiaoreg[4] & M2L17;

--M5L20 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~180 at LC4_B26
--operation mode is normal

M5L20 = M5L14 & (G1_sanjiaoreg[4] # M2L17) # !M5L14 & G1_sanjiaoreg[4] & M2L17;


--M5L13 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~147 at LC7_B25
--operation mode is normal

M5L13 = M5L10 $ G1_sanjiaoreg[3] $ M2L13;

--M5L15 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~181 at LC7_B25
--operation mode is normal

M5L15 = M5L10 $ G1_sanjiaoreg[3] $ M2L13;


--M5L14 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~151 at LC1_B25
--operation mode is normal

M5L14 = M5L10 & (G1_sanjiaoreg[3] # M2L13) # !M5L10 & G1_sanjiaoreg[3] & M2L13;

--M5L16 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~182 at LC1_B25
--operation mode is normal

M5L16 = M5L10 & (G1_sanjiaoreg[3] # M2L13) # !M5L10 & G1_sanjiaoreg[3] & M2L13;


--M5L9 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~155 at LC1_B31
--operation mode is normal

M5L9 = M5L6 $ G1_sanjiaoreg[2] $ M2L9;

--M5L11 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~183 at LC1_B31
--operation mode is normal

M5L11 = M5L6 $ G1_sanjiaoreg[2] $ M2L9;


--M5L10 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~159 at LC3_B31
--operation mode is normal

M5L10 = M5L6 & (G1_sanjiaoreg[2] # M2L9) # !M5L6 & G1_sanjiaoreg[2] & M2L9;

--M5L12 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~184 at LC3_B31
--operation mode is normal

M5L12 = M5L6 & (G1_sanjiaoreg[2] # M2L9) # !M5L6 & G1_sanjiaoreg[2] & M2L9;


--M5L5 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~163 at LC4_B32
--operation mode is normal

M5L5 = M5L2 $ G1_sanjiaoreg[1] $ M2L5;

--M5L7 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~185 at LC4_B32
--operation mode is normal

M5L7 = M5L2 $ G1_sanjiaoreg[1] $ M2L5;


--M5L6 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~167 at LC1_B32
--operation mode is normal

M5L6 = M5L2 & (G1_sanjiaoreg[1] # M2L5) # !M5L2 & G1_sanjiaoreg[1] & M2L5;

--M5L8 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~186 at LC1_B32
--operation mode is normal

M5L8 = M5L2 & (G1_sanjiaoreg[1] # M2L5) # !M5L2 & G1_sanjiaoreg[1] & M2L5;


--M5L1 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~170 at LC3_B32
--operation mode is normal

M5L1 = G1_sanjiaoreg[0] $ M2L1;

--M5L3 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~187 at LC3_B32
--operation mode is normal

M5L3 = G1_sanjiaoreg[0] $ M2L1;


--M5L2 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~173 at LC5_B32
--operation mode is normal

M5L2 = G1_sanjiaoreg[0] & M2L1;

--M5L4 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~188 at LC5_B32
--operation mode is normal

M5L4 = G1_sanjiaoreg[0] & M2L1;


--P3_q[5] is lpm_rom_sanjiao:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[5] at EC11_B
P3_q[5]_clock_0 = GLOBAL(B1_FP2);
P3_q[5]_clock_1 = GLOBAL(B1_FP2);
P3_q[5]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P3_q[5]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P3_q[5] = MEMORY_SEGMENT(, , P3_q[5]_clock_0, P3_q[5]_clock_1, , , , , P3_q[5]_write_address, P3_q[5]_read_address);


--G1_sanjiaoreg[5] is PathSel:inst5|sanjiaoreg[5] at LC5_B26
--operation mode is normal

G1_sanjiaoreg[5] = PathSel[2] & P3_q[5];

--G1L39 is PathSel:inst5|sanjiaoreg[5]~58 at LC5_B26
--operation mode is normal

G1L39 = PathSel[2] & P3_q[5];


--M11_cs_buffer[12] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[12] at LC8_D16
--operation mode is arithmetic

M11_cs_buffer[12] = B1_PAREG[18] $ B1_PASTEP[18] $ !M11_cout[11];

--M11L45 is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[12]~336 at LC8_D16
--operation mode is arithmetic

M11L45 = B1_PAREG[18] $ B1_PASTEP[18] $ !M11_cout[11];

--M11_cout[12] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[12] at LC8_D16
--operation mode is arithmetic

M11_cout[12] = CARRY(B1_PAREG[18] & (M11_cout[11] # !B1_PASTEP[18]) # !B1_PAREG[18] & !B1_PASTEP[18] & M11_cout[11]);


--M11_cs_buffer[13] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[13] at LC1_D18
--operation mode is arithmetic

M11_cs_buffer[13] = B1_PAREG[19] $ B1_PASTEP[19] $ M11_cout[12];

--M11L47 is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[13]~337 at LC1_D18
--operation mode is arithmetic

M11L47 = B1_PAREG[19] $ B1_PASTEP[19] $ M11_cout[12];

--M11_cout[13] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[13] at LC1_D18
--operation mode is arithmetic

M11_cout[13] = CARRY(B1_PAREG[19] & (B1_PASTEP[19] # M11_cout[12]) # !B1_PAREG[19] & B1_PASTEP[19] & M11_cout[12]);


--M11_cs_buffer[14] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[14] at LC2_D18
--operation mode is arithmetic

M11_cs_buffer[14] = B1_PAREG[20] $ B1_PASTEP[20] $ M11_cout[13];

--M11L49 is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[14]~338 at LC2_D18
--operation mode is arithmetic

M11L49 = B1_PAREG[20] $ B1_PASTEP[20] $ M11_cout[13];

--M11_cout[14] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[14] at LC2_D18
--operation mode is arithmetic

M11_cout[14] = CARRY(B1_PAREG[20] & (B1_PASTEP[20] # M11_cout[13]) # !B1_PAREG[20] & B1_PASTEP[20] & M11_cout[13]);


--M11_cs_buffer[15] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[15] at LC3_D18
--operation mode is arithmetic

M11_cs_buffer[15] = B1_PAREG[21] $ B1_PASTEP[21] $ M11_cout[14];

--M11L51 is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[15]~339 at LC3_D18
--operation mode is arithmetic

M11L51 = B1_PAREG[21] $ B1_PASTEP[21] $ M11_cout[14];

--M11_cout[15] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[15] at LC3_D18
--operation mode is arithmetic

M11_cout[15] = CARRY(B1_PAREG[21] & (B1_PASTEP[21] # M11_cout[14]) # !B1_PAREG[21] & B1_PASTEP[21] & M11_cout[14]);


--M11_cs_buffer[16] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[16] at LC4_D18
--operation mode is arithmetic

M11_cs_buffer[16] = B1_PAREG[22] $ B1_PASTEP[22] $ M11_cout[15];

--M11L53 is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[16]~340 at LC4_D18
--operation mode is arithmetic

M11L53 = B1_PAREG[22] $ B1_PASTEP[22] $ M11_cout[15];

--M11_cout[16] is PhaseAcc:inst|lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[16] at LC4_D18
--operation mode is arithmetic

M11_cout[16] = CARRY(B1_PAREG[22] & (B1_PASTEP[22] # M11_cout[15]) # !B1_PAREG[22] & B1_PASTEP[22] & M11_cout[15]);


--P3_q[4] is lpm_rom_sanjiao:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[4] at EC3_B
P3_q[4]_clock_0 = GLOBAL(B1_FP2);
P3_q[4]_clock_1 = GLOBAL(B1_FP2);
P3_q[4]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P3_q[4]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P3_q[4] = MEMORY_SEGMENT(, , P3_q[4]_clock_0, P3_q[4]_clock_1, , , , , P3_q[4]_write_address, P3_q[4]_read_address);


--G1_sanjiaoreg[4] is PathSel:inst5|sanjiaoreg[4] at LC6_B26
--operation mode is normal

G1_sanjiaoreg[4] = P3_q[4] & PathSel[2];

--G1L37 is PathSel:inst5|sanjiaoreg[4]~59 at LC6_B26
--operation mode is normal

G1L37 = P3_q[4] & PathSel[2];


--P3_q[3] is lpm_rom_sanjiao:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[3] at EC14_B
P3_q[3]_clock_0 = GLOBAL(B1_FP2);
P3_q[3]_clock_1 = GLOBAL(B1_FP2);
P3_q[3]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P3_q[3]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P3_q[3] = MEMORY_SEGMENT(, , P3_q[3]_clock_0, P3_q[3]_clock_1, , , , , P3_q[3]_write_address, P3_q[3]_read_address);


--G1_sanjiaoreg[3] is PathSel:inst5|sanjiaoreg[3] at LC2_B32
--operation mode is normal

G1_sanjiaoreg[3] = P3_q[3] & PathSel[2];

--G1L35 is PathSel:inst5|sanjiaoreg[3]~60 at LC2_B32
--operation mode is normal

G1L35 = P3_q[3] & PathSel[2];


--P3_q[2] is lpm_rom_sanjiao:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[2] at EC12_D
P3_q[2]_clock_0 = GLOBAL(B1_FP2);
P3_q[2]_clock_1 = GLOBAL(B1_FP2);
P3_q[2]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P3_q[2]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P3_q[2] = MEMORY_SEGMENT(, , P3_q[2]_clock_0, P3_q[2]_clock_1, , , , , P3_q[2]_write_address, P3_q[2]_read_address);


--G1_sanjiaoreg[2] is PathSel:inst5|sanjiaoreg[2] at LC4_B31
--operation mode is normal

G1_sanjiaoreg[2] = P3_q[2] & PathSel[2];

--G1L33 is PathSel:inst5|sanjiaoreg[2]~61 at LC4_B31
--operation mode is normal

G1L33 = P3_q[2] & PathSel[2];


--P3_q[1] is lpm_rom_sanjiao:inst3|lpm_rom:lpm_rom_component|altrom:srom|q[1] at EC7_B
P3_q[1]_clock_0 = GLOBAL(B1_FP2);
P3_q[1]_clock_1 = GLOBAL(B1_FP2);
P3_q[1]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P3_q[1]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P3_q[1] = MEMORY_SEGMENT(, , P3_q[1]_clock_0, P3_q[1]_clock_1, , , , , P3_q[1]_write_address, P3_q[1]_read_address);