dds.fit.eqn

利用FPGA的资源实现任意波形的产生

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--K3_unreg_res_node[8] is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|unreg_res_node[8] at LC5_B34
--operation mode is normal

K3_unreg_res_node[8] = M5L26 $ M8L26;

--K3L3 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|unreg_res_node[8]~22 at LC5_B34
--operation mode is normal

K3L3 = M5L26 $ M8L26;


--M8L25 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~83 at LC1_B34
--operation mode is normal

M8L25 = M8L22 $ M5L25;

--M8L27 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~133 at LC1_B34
--operation mode is normal

M8L27 = M8L22 $ M5L25;


--M8L26 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~86 at LC2_B34
--operation mode is normal

M8L26 = M8L22 & M5L25;

--M8L28 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]~134 at LC2_B34
--operation mode is normal

M8L28 = M8L22 & M5L25;


--M8L21 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~90 at LC6_B34
--operation mode is normal

M8L21 = M8L18 $ G1_fangboreg[5] $ M5L21;

--M8L23 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~135 at LC6_B34
--operation mode is normal

M8L23 = M8L18 $ G1_fangboreg[5] $ M5L21;


--M8L22 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~94 at LC3_B34
--operation mode is normal

M8L22 = M8L18 & (G1_fangboreg[5] # M5L21) # !M8L18 & G1_fangboreg[5] & M5L21;

--M8L24 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~136 at LC3_B34
--operation mode is normal

M8L24 = M8L18 & (G1_fangboreg[5] # M5L21) # !M8L18 & G1_fangboreg[5] & M5L21;


--M8L17 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~98 at LC4_B25
--operation mode is normal

M8L17 = M8L14 $ G1_fangboreg[4] $ M5L17;

--M8L19 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~137 at LC4_B25
--operation mode is normal

M8L19 = M8L14 $ G1_fangboreg[4] $ M5L17;


--M8L18 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~102 at LC3_B25
--operation mode is normal

M8L18 = M8L14 & (G1_fangboreg[4] # M5L17) # !M8L14 & G1_fangboreg[4] & M5L17;

--M8L20 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~138 at LC3_B25
--operation mode is normal

M8L20 = M8L14 & (G1_fangboreg[4] # M5L17) # !M8L14 & G1_fangboreg[4] & M5L17;


--M8L13 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~106 at LC8_B25
--operation mode is normal

M8L13 = M8L10 $ G1_fangboreg[3] $ M5L13;

--M8L15 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~139 at LC8_B25
--operation mode is normal

M8L15 = M8L10 $ G1_fangboreg[3] $ M5L13;


--M8L14 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~110 at LC2_B25
--operation mode is normal

M8L14 = M8L10 & (G1_fangboreg[3] # M5L13) # !M8L10 & G1_fangboreg[3] & M5L13;

--M8L16 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~140 at LC2_B25
--operation mode is normal

M8L16 = M8L10 & (G1_fangboreg[3] # M5L13) # !M8L10 & G1_fangboreg[3] & M5L13;


--M8L9 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~114 at LC8_B20
--operation mode is normal

M8L9 = M8L6 $ G1_fangboreg[2] $ M5L9;

--M8L11 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~141 at LC8_B20
--operation mode is normal

M8L11 = M8L6 $ G1_fangboreg[2] $ M5L9;


--M8L10 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~118 at LC1_B20
--operation mode is normal

M8L10 = M8L6 & (G1_fangboreg[2] # M5L9) # !M8L6 & G1_fangboreg[2] & M5L9;

--M8L12 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~142 at LC1_B20
--operation mode is normal

M8L12 = M8L6 & (G1_fangboreg[2] # M5L9) # !M8L6 & G1_fangboreg[2] & M5L9;


--M8L5 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~122 at LC6_B23
--operation mode is normal

M8L5 = M8L2 $ G1_fangboreg[1] $ M5L5;

--M8L7 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~143 at LC6_B23
--operation mode is normal

M8L7 = M8L2 $ G1_fangboreg[1] $ M5L5;


--M8L6 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~126 at LC1_B23
--operation mode is normal

M8L6 = M8L2 & (G1_fangboreg[1] # M5L5) # !M8L2 & G1_fangboreg[1] & M5L5;

--M8L8 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~144 at LC1_B23
--operation mode is normal

M8L8 = M8L2 & (G1_fangboreg[1] # M5L5) # !M8L2 & G1_fangboreg[1] & M5L5;


--M8L1 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~129 at LC8_B23
--operation mode is normal

M8L1 = G1_fangboreg[0] $ M5L1;

--M8L3 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~145 at LC8_B23
--operation mode is normal

M8L3 = G1_fangboreg[0] $ M5L1;


--M8L2 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~132 at LC2_B23
--operation mode is normal

M8L2 = G1_fangboreg[0] # M5L1;

--M8L4 is PathSel:inst5|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~146 at LC2_B23
--operation mode is normal

M8L4 = G1_fangboreg[0] # M5L1;


--P1_q[5] is lpm_rom_fangbo:inst4|lpm_rom:lpm_rom_component|altrom:srom|q[5] at EC8_D
P1_q[5]_clock_0 = GLOBAL(B1_FP2);
P1_q[5]_clock_1 = GLOBAL(B1_FP2);
P1_q[5]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P1_q[5]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P1_q[5] = MEMORY_SEGMENT(, , P1_q[5]_clock_0, P1_q[5]_clock_1, , , , , P1_q[5]_write_address, P1_q[5]_read_address);


--G1_fangboreg[5] is PathSel:inst5|fangboreg[5] at LC4_B34
--operation mode is normal

G1_fangboreg[5] = PathSel[3] & P1_q[5];

--G1L13 is PathSel:inst5|fangboreg[5]~65 at LC4_B34
--operation mode is normal

G1L13 = PathSel[3] & P1_q[5];


--P1_q[4] is lpm_rom_fangbo:inst4|lpm_rom:lpm_rom_component|altrom:srom|q[4] at EC1_B
P1_q[4]_clock_0 = GLOBAL(B1_FP2);
P1_q[4]_clock_1 = GLOBAL(B1_FP2);
P1_q[4]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P1_q[4]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P1_q[4] = MEMORY_SEGMENT(, , P1_q[4]_clock_0, P1_q[4]_clock_1, , , , , P1_q[4]_write_address, P1_q[4]_read_address);


--G1_fangboreg[4] is PathSel:inst5|fangboreg[4] at LC5_B25
--operation mode is normal

G1_fangboreg[4] = P1_q[4] & PathSel[3];

--G1L11 is PathSel:inst5|fangboreg[4]~66 at LC5_B25
--operation mode is normal

G1L11 = P1_q[4] & PathSel[3];


--P1_q[3] is lpm_rom_fangbo:inst4|lpm_rom:lpm_rom_component|altrom:srom|q[3] at EC9_B
P1_q[3]_clock_0 = GLOBAL(B1_FP2);
P1_q[3]_clock_1 = GLOBAL(B1_FP2);
P1_q[3]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P1_q[3]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P1_q[3] = MEMORY_SEGMENT(, , P1_q[3]_clock_0, P1_q[3]_clock_1, , , , , P1_q[3]_write_address, P1_q[3]_read_address);


--G1_fangboreg[3] is PathSel:inst5|fangboreg[3] at LC6_B25
--operation mode is normal

G1_fangboreg[3] = P1_q[3] & PathSel[3];

--G1L9 is PathSel:inst5|fangboreg[3]~67 at LC6_B25
--operation mode is normal

G1L9 = P1_q[3] & PathSel[3];


--P1_q[2] is lpm_rom_fangbo:inst4|lpm_rom:lpm_rom_component|altrom:srom|q[2] at EC5_B
P1_q[2]_clock_0 = GLOBAL(B1_FP2);
P1_q[2]_clock_1 = GLOBAL(B1_FP2);
P1_q[2]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P1_q[2]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P1_q[2] = MEMORY_SEGMENT(, , P1_q[2]_clock_0, P1_q[2]_clock_1, , , , , P1_q[2]_write_address, P1_q[2]_read_address);


--G1_fangboreg[2] is PathSel:inst5|fangboreg[2] at LC2_B20
--operation mode is normal

G1_fangboreg[2] = P1_q[2] & PathSel[3];

--G1L7 is PathSel:inst5|fangboreg[2]~68 at LC2_B20
--operation mode is normal

G1L7 = P1_q[2] & PathSel[3];


--P1_q[1] is lpm_rom_fangbo:inst4|lpm_rom:lpm_rom_component|altrom:srom|q[1] at EC12_B
P1_q[1]_clock_0 = GLOBAL(B1_FP2);
P1_q[1]_clock_1 = GLOBAL(B1_FP2);
P1_q[1]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P1_q[1]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P1_q[1] = MEMORY_SEGMENT(, , P1_q[1]_clock_0, P1_q[1]_clock_1, , , , , P1_q[1]_write_address, P1_q[1]_read_address);


--G1_fangboreg[1] is PathSel:inst5|fangboreg[1] at LC3_B23
--operation mode is normal

G1_fangboreg[1] = P1_q[1] & PathSel[3];

--G1L5 is PathSel:inst5|fangboreg[1]~69 at LC3_B23
--operation mode is normal

G1L5 = P1_q[1] & PathSel[3];


--P1_q[0] is lpm_rom_fangbo:inst4|lpm_rom:lpm_rom_component|altrom:srom|q[0] at EC6_B
P1_q[0]_clock_0 = GLOBAL(B1_FP2);
P1_q[0]_clock_1 = GLOBAL(B1_FP2);
P1_q[0]_write_address = WR_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P1_q[0]_read_address = RD_ADDR(B1_PAREG[18], B1_PAREG[19], B1_PAREG[20], B1_PAREG[21], B1_PAREG[22], B1_PAREG[23], B1_PAREG[23], B1_PAREG[23]);
P1_q[0] = MEMORY_SEGMENT(, , P1_q[0]_clock_0, P1_q[0]_clock_1, , , , , P1_q[0]_write_address, P1_q[0]_read_address);


--G1_fangboreg[0] is PathSel:inst5|fangboreg[0] at LC4_B23
--operation mode is normal

G1_fangboreg[0] = P1_q[0] & PathSel[3];

--G1L3 is PathSel:inst5|fangboreg[0]~70 at LC4_B23
--operation mode is normal

G1L3 = P1_q[0] & PathSel[3];


--M5L25 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~124 at LC7_B34
--operation mode is normal

M5L25 = M5L22 $ M2L22;

--M5L27 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~175 at LC7_B34
--operation mode is normal

M5L27 = M5L22 $ M2L22;


--M5L26 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~127 at LC8_B34
--operation mode is normal

M5L26 = M5L22 & M2L22;

--M5L28 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]~176 at LC8_B34
--operation mode is normal

M5L28 = M5L22 & M2L22;


--M5L21 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~131 at LC3_B26
--operation mode is normal

M5L21 = M5L18 $ G1_sanjiaoreg[5] $ M2L21;

--M5L23 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~177 at LC3_B26
--operation mode is normal

M5L23 = M5L18 $ G1_sanjiaoreg[5] $ M2L21;


--M5L22 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~135 at LC2_B26
--operation mode is normal

M5L22 = M5L18 & (G1_sanjiaoreg[5] # M2L21) # !M5L18 & G1_sanjiaoreg[5] & M2L21;

--M5L24 is PathSel:inst5|lpm_add_sub:add_rtl_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~178 at LC2_B26
--operation mode is normal

M5L24 = M5L18 & (G1_sanjiaoreg[5] # M2L21) # !M5L18 & G1_sanjiaoreg[5] & M2L21;


--B1_FP2 is PhaseAcc:inst|FP2 at LC1_J24
--operation mode is normal

B1_FP2_lut_out = !B1_FP2;
B1_FP2 = DFFEA(B1_FP2_lut_out, !GLOBAL(CLK), GLOBAL(RST), , , , );

--B1L4Q is PhaseAcc:inst|FP2~1 at LC1_J24
--operation mode is normal

B1L4Q = B1_FP2;