📄 rtc.lst
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Archelon msp430 Assembler Version 1.60 2005/02/09 File E:\Developing\freq\Anti-Tamperring Emeter\key_check_emeter\source_file\rtc.asm Page 1
1 ; Archelon URCC C 3.20 2005/04/19
2 ; MSP430 CIF 2005/04/06
3 ; Compiled "E:\Developing\freq\Anti-Tamperring Emeter\key_check_emeter\source_file\rtc.c" Fri Sep 09 15:21:04 2005
4 ;
5 .dbgseg dbg_syms
0000 6 .align 0x2
0000 6c69662e 7 .long 0x6c69662e
0004 00000065 8 .long 0x65
0008 00000001 9 .long 0x1
000c 00000000 10 .long 0x0
0010 0167fffe 11 .long 0x167fffe
0014 00000000 12 .long 0x0
0018 0000011c 13 .long DBG5
001c 00000000 14 .long 0x0
0020 00000000 15 .long 0x0
0024 00000000 16 .long 0x0
17 ; __builtin__ unsigned short _BIS_SR(unsigned short);
18 ; __builtin__ unsigned short _BIC_SR(unsigned short);
19 ; __builtin__ unsigned short _BIS_SR_IRQ(unsigned short);
20 ; __builtin__ unsigned short _BIC_SR_IRQ(unsigned short);
21 ; __builtin__ void _DINT(void);
22 ; __builtin__ void _EINT(void);
23 ; __builtin__ void _NOP(void);
24 ; __builtin__ void _OPC(const unsigned short op);
25 ; __builtin__ short _SWPB(short);
26 ; __builtin__ long _SWPB_LONG(long);
27 ; __builtin__ float _SWPB_FLOAT(float);
28 ; sfrb IE1 = (0x0000) ;
29 ; sfrb IFG1 = (0x0002) ;
30 ; sfrb ME1 = (0x0004) ;
31 ; sfrb IE2 = (0x0001) ;
32 ; sfrb IFG2 = (0x0003) ;
33 ; sfrw WDTCTL = (0x0120) ;
34 ; const sfrb P1IN = (0x0020) ;
35 ; sfrb P1OUT = (0x0021) ;
36 ; sfrb P1DIR = (0x0022) ;
37 ; sfrb P1IFG = (0x0023) ;
38 ; sfrb P1IES = (0x0024) ;
39 ; sfrb P1IE = (0x0025) ;
40 ; sfrb P1SEL = (0x0026) ;
41 ; const sfrb P2IN = (0x0028) ;
42 ; sfrb P2OUT = (0x0029) ;
43 ; sfrb P2DIR = (0x002A) ;
44 ; sfrb P2IFG = (0x002B) ;
45 ; sfrb P2IES = (0x002C) ;
46 ; sfrb P2IE = (0x002D) ;
47 ; sfrb P2SEL = (0x002E) ;
48 ; sfrb BTCTL = (0x0040) ;
49 ; sfrb BTCNT1 = (0x0046) ;
50 ; sfrb BTCNT2 = (0x0047) ;
51 ; sfrb SCFI0 = (0x0050) ;
52 ; sfrb SCFI1 = (0x0051) ;
53 ; sfrb SCFQCTL = (0x0052) ;
54 ; sfrb FLL_CTL0 = (0x0053) ;
55 ; sfrb FLL_CTL1 = (0x0054) ;
56 ; sfrb SVSCTL = (0x0056) ;
57 ; sfrb LCDCTL = (0x0090) ;
58 ; sfrb LCDM1 = (0x0091) ;
59 ; sfrb LCDM2 = (0x0092) ;
60 ; sfrb LCDM3 = (0x0093) ;
61 ; sfrb LCDM4 = (0x0094) ;
62 ; sfrb LCDM5 = (0x0095) ;
63 ; sfrb LCDM6 = (0x0096) ;
64 ; sfrb LCDM7 = (0x0097) ;
65 ; sfrb LCDM8 = (0x0098) ;
66 ; sfrb LCDM9 = (0x0099) ;
67 ; sfrb LCDM10 = (0x009A) ;
68 ; sfrb LCDM11 = (0x009B) ;
69 ; sfrb LCDM12 = (0x009C) ;
70 ; sfrb LCDM13 = (0x009D) ;
71 ; sfrb LCDM14 = (0x009E) ;
72 ; sfrb LCDM15 = (0x009F) ;
73 ; sfrb LCDM16 = (0x00A0) ;
74 ; sfrb LCDM17 = (0x00A1) ;
75 ; sfrb LCDM18 = (0x00A2) ;
76 ; sfrb LCDM19 = (0x00A3) ;
77 ; sfrb LCDM20 = (0x00A4) ;
78 ; sfrb U0CTL = (0x0070) ;
79 ; sfrb U0TCTL = (0x0071) ;
80 ; sfrb U0RCTL = (0x0072) ;
81 ; sfrb U0MCTL = (0x0073) ;
82 ; sfrb U0BR0 = (0x0074) ;
83 ; sfrb U0BR1 = (0x0075) ;
84 ; const sfrb U0RXBUF = (0x0076) ;
85 ; sfrb U0TXBUF = (0x0077) ;
86 ; const sfrw TAIV = (0x012E) ;
87 ; sfrw TACTL = (0x0160) ;
88 ; sfrw TACCTL0 = (0x0162) ;
89 ; sfrw TACCTL1 = (0x0164) ;
90 ; sfrw TACCTL2 = (0x0166) ;
91 ; sfrw TAR = (0x0170) ;
92 ; sfrw TACCR0 = (0x0172) ;
93 ; sfrw TACCR1 = (0x0174) ;
94 ; sfrw TACCR2 = (0x0176) ;
95 ; sfrw FCTL1 = (0x0128) ;
96 ; sfrw FCTL2 = (0x012A) ;
97 ; sfrw FCTL3 = (0x012C) ;
98 ; sfrw MPY = (0x0130) ;
99 ; sfrw MPYS = (0x0132) ;
100 ; sfrw MAC = (0x0134) ;
101 ; sfrw MACS = (0x0136) ;
102 ; sfrw OP2 = (0x0138) ;
103 ; sfrw RESLO = (0x013A) ;
104 ; sfrw RESHI = (0x013C) ;
105 ; const sfrw SUMEXT = (0x013E) ;
106 ; sfrb SD16INCTL0 = (0x00B0) ;
107 ; sfrb SD16INCTL1 = (0x00B1) ;
108 ; sfrb SD16INCTL2 = (0x00B2) ;
109 ; sfrb SD16PRE0 = (0x00B8) ;
110 ; sfrb SD16PRE1 = (0x00B9) ;
111 ; sfrb SD16PRE2 = (0x00BA) ;
112 ; sfrb SD16TRIM1 = (0x00BF) ;
113 ; sfrb SD16CONF0 = (0x00B7) ;
114 ; sfrb SD16CONF1 = (0x00BF) ;
115 ; sfrw SD16CTL = (0x0100) ;
116 ; sfrw SD16CCTL0 = (0x0102) ;
117 ; sfrw SD16CCTL1 = (0x0104) ;
118 ; sfrw SD16CCTL2 = (0x0106) ;
119 ; sfrw SD16IV = (0x0110) ;
120 ; sfrw SD16MEM0 = (0x0112) ;
121 ; sfrw SD16MEM1 = (0x0114) ;
122 ; sfrw SD16MEM2 = (0x0116) ;
123 ; sfrw ESPCTL = (0x0150) ;
124 ; sfrw MBCTL = (0x0152) ;
125 ; sfrw MBIN0 = (0x0154) ;
126 ; sfrw MBIN1 = (0x0156) ;
127 ; sfrw MBOUT0 = (0x0158) ;
128 ; sfrw MBOUT1 = (0x015A) ;
129 ; const sfrw RET0 = (0x01C0) ;
130 ; const sfrw RET1 = (0x01C2) ;
131 ; const sfrw RET2 = (0x01C4) ;
132 ; const sfrw RET3 = (0x01C6) ;
133 ; const sfrw RET4 = (0x01C8) ;
134 ; const sfrw RET5 = (0x01CA) ;
135 ; const sfrw RET6 = (0x01CC) ;
136 ; const sfrw RET7 = (0x01CE) ;
137 ; const sfrw RET8 = (0x01D0) ;
138 ; const sfrw RET9 = (0x01D2) ;
139 ; const sfrw RET10 = (0x01D4) ;
140 ; const sfrw RET11 = (0x01D6) ;
141 ; const sfrw RET12 = (0x01D8) ;
142 ; const sfrw RET13 = (0x01DA) ;
143 ; const sfrw RET14 = (0x01DC) ;
144 ; const sfrw RET15 = (0x01DE) ;
145 ; const sfrw RET16 = (0x01E0) ;
146 ; const sfrw RET17 = (0x01E2) ;
147 ; const sfrw RET18 = (0x01E4) ;
148 ; const sfrw RET19 = (0x01E6) ;
149 ; const sfrw RET20 = (0x01E8) ;
150 ; const sfrw RET21 = (0x01EA) ;
151 ; const sfrw RET22 = (0x01EC) ;
152 ; const sfrw RET23 = (0x01EE) ;
153 ; const sfrw RET24 = (0x01F0) ;
154 ; const sfrw RET25 = (0x01F2) ;
155 ; const sfrw RET26 = (0x01F4) ;
156 ; const sfrw RET27 = (0x01F6) ;
157 ; const sfrw RET28 = (0x01F8) ;
158 ; const sfrw RET29 = (0x01FA) ;
159 ; const sfrw RET30 = (0x01FC) ;
160 ; const sfrw RET31 = (0x01FE) ;
161 ; typedef unsigned char uint8;
162 ; uint8 size 1
163 ; typedef signed char int8;
164 ; int8 size 1
165 ; typedef unsigned int uint16;
166 ; uint16 size 2
167 ; typedef signed int int16;
168 ; int16 size 2
169 ; typedef unsigned long uint32;
170 ; uint32 size 4
171 ; typedef signed long int32;
172 ; int32 size 4
173 ; typedef unsigned char uint8_t;
174 ; uint8_t size 1
175 ; typedef signed char int8_t;
176 ; int8_t size 1
177 ; typedef unsigned int uint16_t;
178 ; uint16_t size 2
179 ; typedef signed int int16_t;
180 ; int16_t size 2
181 ; typedef unsigned long uint32_t;
182 ; uint32_t size 4
183 ; typedef signed long int32_t;
184 ; int32_t size 4
185 ; extern const unsigned char lcd_digit_table[];
186 ; struct emeter_var
187 ; {
188 ; uint16 ui_meter_status;
189 ; uint16 ui_anti_tamperring_status;
190 ; uint16 ui_firmware_version;
191 ; uint8 uc_display_stage;
192 ; uint16 ui_sec_count;
193 ; uint16 ui_main_frequency;
194 ; uint16 ui_power_factor;
195 ; int16 i_last_temperature;
196 ; int16 i_temperature;
197 ; int16 i_temperature_offset;
198 ; uint16 ui_current_IRMS;
199 ; uint16 ui_voltage_V1RMS;
200 ; float f_total_energy;
201 ; uint32 ul_total_power;
202 ; uint32 ul_act_power_counter;
203 ; uint32 ul_act_power1;
204 ; uint32 ul_act_power2;
205 ; uint32 ul_react_power;
206 ; uint32 ul_app_power;
207 ; float f_re_total_power;
208 ; uint8 ucFlashOperated[2];
209 ; float f_Cz1;
210 ; float f_Cz2;
211 ; uint16 ui_GainCorr1;
212 ; uint16 ui_GainCorr2;
213 ; int32 l_PowerOffset1;
214 ; int32 l_PowerOffset2;
215 ; float f_PhaseCorr1;
216 ; float f_PhaseCorr2;
217 ; uint16 ui_SD16_CurrentCorr1;
218 ; uint16 ui_SD16_CurrentCorr2;
219 ; uint16 ui_SD16_VoltageCorr1;
220 ; uint16 ul_TempSampleOffset;
221 ; uint8 ucCalibrationMode;
222 ; uint8 ucCalibrationOption;
223 ; uint8 uc_pout_hc595;
224 ; uint8 uc_restart_esp_delay;
225 ; uint8 uc_lcd_remaining_times;
226 ; uint8 uc_switch_delay_counter;
227 ; uint8 display_stage;
228 ; };
229 ; extern struct emeter_var emeter;
230 ; union signed_long_word
231 ; {
232 ; int32 l;
233 ; uint16 w[2];
234 ; };
235 ; extern union signed_long_word ds;
236 ; extern uint32 ul_total_power_infact;
237 ; extern uint16 ui_step_counter;
238 ; struct current_sensor_parms_s
239 ; {
240 ; uint16 V_rms;
241 ; uint16 I_rms;
242 ; int32_t I_dc_estimate;
243 ; int16_t P_accum[3];
244 ; int16_t P_accum_logged[3];
245 ; int16_t I_sq_accum[3];
246 ; int16_t I_sq_accum_logged[3];
247 ; int16_t sample_count;
248 ; int16_t sample_count_logged;
249 ; int16_t fir_beta;
250 ; int16_t fir_step;
251 ; int16_t fir_gain;
252 ; int16_t I_history[2];
253 ; int8_t I_endstops;
254 ; };
255 ; struct phase_parms_s
256 ; {
257 ; uint16_t V_rms;
258 ; uint16_t I_rms;
259 ; int32_t V_dc_estimate[2];
260 ; int16_t V_history[4];
261 ; int16_t V_sq_accum[3];
262 ; int16_t V_sq_accum_logged[3];
263 ; struct current_sensor_parms_s current;
264 ; struct current_sensor_parms_s neutral;
265 ; int16_t sample_count;
266 ; int16_t sample_count_logged;
267 ; uint16_t status;
268 ; int8_t V_endstops;
269 ; int8_t V_history_index;
270 ; };
271 ; extern struct phase_parms_s *phase;
272 ; enum
273 ; {
274 ; DISPLAY_STAGE_ACT_ENERGY_1 = 1,
275 ; DISPLAY_STAGE_ACT_ENERGY_2,
276 ; DISPLAY_STAGE_CURRENT,
277 ; DISPLAY_STAGE_VOLTAGE,
278 ; DISPLAY_STAGE_FREQUENCY,
279 ; DISPLAY_STAGE_POWERFACTOR,
280 ; DISPLAY_STAGE_REACT_ENERGY,
281 ; DISPLAY_STAGE_APP_ENERGY,
282 ; DISPLAY_STAGE_TEMPERATURE,
283 ; DISPLAY_STAGE_TIME,
284 ; DISPLAY_STAGE_DATE,
285 ; DISPLAY_STAGE_TEST1,
286 ; DISPLAY_STAGE_TEST2,
287 ; DISPLAY_STAGE_TEST3,
288 ; DISPLAY_STAGE_TEST4,
289 ; DISPLAY_STAGE_TEST5,
290 ; DISPLAY_STAGE_TEST6,
291 ; DISPLAY_STAGE_TEST7,
292 ; DISPLAY_STAGE_TEST8,
293 ; DISPLAY_STAGE_TEST9,
294 ; DISPLAY_STAGE_LAST
295 ; };
296 ; struct rtc_s
297 ; {
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