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📄 rtc.asm

📁 FE42X单相防窃电电表DEMO(编译器 AQ430 AQ430 V2.0.6.5)
💻 ASM
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; Archelon URCC C 3.20 2005/04/19
; MSP430 CIF 2005/04/06
; Compiled "E:\Developing\freq\Anti-Tamperring Emeter\key_check_emeter\source_file\rtc.c" Fri Sep 09 15:21:04 2005
; 
	.dbgseg dbg_syms
	.align 0x2
	.long 0x6c69662e
	.long 0x65
	.long 0x1
	.long 0x0
	.long 0x167fffe
	.long 0x0
	.long DBG5
	.long 0x0
	.long 0x0
	.long 0x0
; __builtin__ unsigned short _BIS_SR(unsigned short);
; __builtin__ unsigned short _BIC_SR(unsigned short);
; __builtin__ unsigned short _BIS_SR_IRQ(unsigned short);
; __builtin__ unsigned short _BIC_SR_IRQ(unsigned short);
;  __builtin__ void _DINT(void);
; __builtin__ void _EINT(void);
; __builtin__ void _NOP(void);
; __builtin__ void _OPC(const unsigned short op);
; __builtin__ short _SWPB(short);  
; __builtin__ long _SWPB_LONG(long);  
; __builtin__ float _SWPB_FLOAT(float);  
; sfrb    IE1               = (0x0000) ;
; sfrb    IFG1              = (0x0002) ;
; sfrb    ME1               = (0x0004) ;
; sfrb    IE2               = (0x0001) ;
; sfrb    IFG2              = (0x0003) ;
; sfrw    WDTCTL            = (0x0120) ;
; const sfrb P1IN           = (0x0020) ;
; sfrb    P1OUT             = (0x0021) ;
; sfrb    P1DIR             = (0x0022) ;
; sfrb    P1IFG             = (0x0023) ;
; sfrb    P1IES             = (0x0024) ;
; sfrb    P1IE              = (0x0025) ;
; sfrb    P1SEL             = (0x0026) ;
; const sfrb P2IN           = (0x0028) ;
; sfrb    P2OUT             = (0x0029) ;
; sfrb    P2DIR             = (0x002A) ;
; sfrb    P2IFG             = (0x002B) ;
; sfrb    P2IES             = (0x002C) ;
; sfrb    P2IE              = (0x002D) ;
; sfrb    P2SEL             = (0x002E) ;
; sfrb    BTCTL             = (0x0040) ;
; sfrb    BTCNT1            = (0x0046) ;
; sfrb    BTCNT2            = (0x0047) ;
; sfrb    SCFI0             = (0x0050) ;
; sfrb    SCFI1             = (0x0051) ;
; sfrb    SCFQCTL           = (0x0052) ;
; sfrb    FLL_CTL0          = (0x0053) ;
; sfrb    FLL_CTL1          = (0x0054) ;
; sfrb    SVSCTL            = (0x0056) ;
; sfrb    LCDCTL            = (0x0090) ;
; sfrb    LCDM1             = (0x0091) ;
; sfrb    LCDM2             = (0x0092) ;
; sfrb    LCDM3             = (0x0093) ;
; sfrb    LCDM4             = (0x0094) ;
; sfrb    LCDM5             = (0x0095) ;
; sfrb    LCDM6             = (0x0096) ;
; sfrb    LCDM7             = (0x0097) ;
; sfrb    LCDM8             = (0x0098) ;
; sfrb    LCDM9             = (0x0099) ;
; sfrb    LCDM10            = (0x009A) ;
; sfrb    LCDM11            = (0x009B) ;
; sfrb    LCDM12            = (0x009C) ;
; sfrb    LCDM13            = (0x009D) ;
; sfrb    LCDM14            = (0x009E) ;
; sfrb    LCDM15            = (0x009F) ;
; sfrb    LCDM16            = (0x00A0) ;
; sfrb    LCDM17            = (0x00A1) ;
; sfrb    LCDM18            = (0x00A2) ;
; sfrb    LCDM19            = (0x00A3) ;
; sfrb    LCDM20            = (0x00A4) ;
; sfrb    U0CTL             = (0x0070) ;
; sfrb    U0TCTL            = (0x0071) ;
; sfrb    U0RCTL            = (0x0072) ;
; sfrb    U0MCTL            = (0x0073) ;
; sfrb    U0BR0             = (0x0074) ;
; sfrb    U0BR1             = (0x0075) ;
; const sfrb U0RXBUF        = (0x0076) ;
; sfrb    U0TXBUF           = (0x0077) ;
; const sfrw TAIV           = (0x012E) ;
; sfrw    TACTL             = (0x0160) ;
; sfrw    TACCTL0           = (0x0162) ;
; sfrw    TACCTL1           = (0x0164) ;
; sfrw    TACCTL2           = (0x0166) ;
; sfrw    TAR               = (0x0170) ;
; sfrw    TACCR0            = (0x0172) ;
; sfrw    TACCR1            = (0x0174) ;
; sfrw    TACCR2            = (0x0176) ;
; sfrw    FCTL1             = (0x0128) ;
; sfrw    FCTL2             = (0x012A) ;
; sfrw    FCTL3             = (0x012C) ;
; sfrw    MPY               = (0x0130) ;
; sfrw    MPYS              = (0x0132) ;
; sfrw    MAC               = (0x0134) ;
; sfrw    MACS              = (0x0136) ;
; sfrw    OP2               = (0x0138) ;
; sfrw    RESLO             = (0x013A) ;
; sfrw    RESHI             = (0x013C) ;
; const sfrw SUMEXT         = (0x013E) ;
; sfrb    SD16INCTL0        = (0x00B0) ;
; sfrb    SD16INCTL1        = (0x00B1) ;
; sfrb    SD16INCTL2        = (0x00B2) ;
; sfrb    SD16PRE0          = (0x00B8) ;
; sfrb    SD16PRE1          = (0x00B9) ;
; sfrb    SD16PRE2          = (0x00BA) ;
; sfrb	SD16TRIM1	      = (0x00BF) ;
; sfrb    SD16CONF0         = (0x00B7) ;
; sfrb    SD16CONF1         = (0x00BF) ;
; sfrw    SD16CTL           = (0x0100) ;
; sfrw    SD16CCTL0         = (0x0102) ;
; sfrw    SD16CCTL1         = (0x0104) ;
; sfrw    SD16CCTL2         = (0x0106) ;
; sfrw    SD16IV            = (0x0110) ;
; sfrw    SD16MEM0          = (0x0112) ;
; sfrw    SD16MEM1          = (0x0114) ;
; sfrw    SD16MEM2          = (0x0116) ;
; sfrw    ESPCTL            = (0x0150) ;
; sfrw    MBCTL             = (0x0152) ;
; sfrw    MBIN0             = (0x0154) ;
; sfrw    MBIN1             = (0x0156) ;
; sfrw    MBOUT0            = (0x0158) ;
; sfrw    MBOUT1            = (0x015A) ;
; const sfrw    RET0        = (0x01C0) ;
; const sfrw    RET1        = (0x01C2) ;
; const sfrw    RET2        = (0x01C4) ;
; const sfrw    RET3        = (0x01C6) ;
; const sfrw    RET4        = (0x01C8) ;
; const sfrw    RET5        = (0x01CA) ;
; const sfrw    RET6        = (0x01CC) ;
; const sfrw    RET7        = (0x01CE) ;
; const sfrw    RET8        = (0x01D0) ;
; const sfrw    RET9        = (0x01D2) ;
; const sfrw    RET10       = (0x01D4) ;
; const sfrw    RET11       = (0x01D6) ;
; const sfrw    RET12       = (0x01D8) ;
; const sfrw    RET13       = (0x01DA) ;
; const sfrw    RET14       = (0x01DC) ;
; const sfrw    RET15       = (0x01DE) ;
; const sfrw    RET16       = (0x01E0) ;
; const sfrw    RET17       = (0x01E2) ;
; const sfrw    RET18       = (0x01E4) ;
; const sfrw    RET19       = (0x01E6) ;
; const sfrw    RET20       = (0x01E8) ;
; const sfrw    RET21       = (0x01EA) ;
; const sfrw    RET22       = (0x01EC) ;
; const sfrw    RET23       = (0x01EE) ;
; const sfrw    RET24       = (0x01F0) ;
; const sfrw    RET25       = (0x01F2) ;
; const sfrw    RET26       = (0x01F4) ;
; const sfrw    RET27       = (0x01F6) ;
; const sfrw    RET28       = (0x01F8) ;
; const sfrw    RET29       = (0x01FA) ;
; const sfrw    RET30       = (0x01FC) ;
; const sfrw    RET31       = (0x01FE) ;
; typedef unsigned char uint8;
; uint8 size 1
; typedef signed char int8;
; int8 size 1
; typedef unsigned int  uint16;
; uint16 size 2
; typedef signed int  int16;
; int16 size 2
; typedef unsigned long  uint32;
; uint32 size 4
; typedef signed long  int32;
; int32 size 4
; typedef unsigned char uint8_t;
; uint8_t size 1
; typedef signed char int8_t;
; int8_t size 1
; typedef unsigned int  uint16_t;
; uint16_t size 2
; typedef signed int  int16_t;
; int16_t size 2
; typedef unsigned long  uint32_t;
; uint32_t size 4
; typedef signed long  int32_t;
; int32_t size 4
; extern const unsigned char lcd_digit_table[];
; struct emeter_var
; {
; 	uint16 ui_meter_status;
; 	uint16 ui_anti_tamperring_status;
; 	uint16 ui_firmware_version;
; 	uint8 uc_display_stage;
; 	uint16 ui_sec_count;
; 	uint16 ui_main_frequency;
;     uint16 ui_power_factor;
;     int16 i_last_temperature;
;     int16 i_temperature;
; 	int16 i_temperature_offset;
; 	uint16 ui_current_IRMS;
; 	uint16 ui_voltage_V1RMS;
; 	float f_total_energy;
; 	uint32 ul_total_power;
; 	uint32 ul_act_power_counter;
; 	uint32 ul_act_power1;
; 	uint32 ul_act_power2;
; 	uint32 ul_react_power;
; 	uint32 ul_app_power;
; 	float f_re_total_power;
; 	uint8 ucFlashOperated[2];
; 	float f_Cz1;  
; 	float f_Cz2;  
; 	uint16 ui_GainCorr1;
; 	uint16 ui_GainCorr2;
; 	int32 l_PowerOffset1;
; 	int32 l_PowerOffset2;
; 	float f_PhaseCorr1;
; 	float f_PhaseCorr2;
; 	uint16 ui_SD16_CurrentCorr1;
; 	uint16 ui_SD16_CurrentCorr2;
; 	uint16 ui_SD16_VoltageCorr1;
; 	uint16 ul_TempSampleOffset;
; 	uint8 ucCalibrationMode;
; 	uint8 ucCalibrationOption;
; 	uint8 uc_pout_hc595;
; 	uint8 uc_restart_esp_delay;
; 	uint8 uc_lcd_remaining_times;
; 	uint8 uc_switch_delay_counter;
; 	uint8 display_stage;
; };
; extern struct emeter_var emeter;
; union signed_long_word
; {
;       int32 l;
;       uint16 w[2];
; };
; extern union signed_long_word ds;
; extern uint32 ul_total_power_infact;
; extern uint16 ui_step_counter;
; struct current_sensor_parms_s
; {
; 	uint16 V_rms;
;     uint16 I_rms;
;     int32_t I_dc_estimate;
;     int16_t P_accum[3];
;     int16_t P_accum_logged[3];
;     int16_t I_sq_accum[3];
;     int16_t I_sq_accum_logged[3];
;     int16_t sample_count;
;     int16_t sample_count_logged;
;     int16_t fir_beta;
;     int16_t fir_step;
;     int16_t fir_gain;
;     int16_t I_history[2];
;     int8_t I_endstops;
; };
; struct phase_parms_s
; {
;     uint16_t V_rms;
;     uint16_t I_rms;
;     int32_t V_dc_estimate[2];
; 	int16_t V_history[4];
;     int16_t V_sq_accum[3];
;     int16_t V_sq_accum_logged[3];
; 	struct current_sensor_parms_s current;
; 	struct current_sensor_parms_s neutral;
;     int16_t sample_count;
;     int16_t sample_count_logged;
;     uint16_t status;
; 	int8_t V_endstops;
; 	int8_t V_history_index;
; };
; extern struct phase_parms_s *phase;
; enum
; {
;     DISPLAY_STAGE_ACT_ENERGY_1 = 1, 
;     DISPLAY_STAGE_ACT_ENERGY_2,     
;     DISPLAY_STAGE_CURRENT,          
; 	DISPLAY_STAGE_VOLTAGE,          
; 	DISPLAY_STAGE_FREQUENCY,        
; 	DISPLAY_STAGE_POWERFACTOR,      
; 	DISPLAY_STAGE_REACT_ENERGY,     
; 	DISPLAY_STAGE_APP_ENERGY,       
; 	DISPLAY_STAGE_TEMPERATURE,      
; 	DISPLAY_STAGE_TIME,				
; 	DISPLAY_STAGE_DATE,				
; 	DISPLAY_STAGE_TEST1,
; 	DISPLAY_STAGE_TEST2,
; 	DISPLAY_STAGE_TEST3,
; 	DISPLAY_STAGE_TEST4,
; 	DISPLAY_STAGE_TEST5,
; 	DISPLAY_STAGE_TEST6,
; 	DISPLAY_STAGE_TEST7,
; 	DISPLAY_STAGE_TEST8,
; 	DISPLAY_STAGE_TEST9,				
;     DISPLAY_STAGE_LAST
; };
; struct  rtc_s
; {
; 	uint8 second;
; 	uint8 minute;
; 	uint8 hour;
; 	uint8 day;
; 	uint8 week;
; 	uint8 month;
; 	uint8 year;
; 	uint8 sumcheck;
; };
; extern struct rtc_s rtc;	
; extern uint32 ul_actensper1;
; extern uint32 ul_actensper2;
; static int32 rtc_correction;
; const int8 month_lengths[13] =
	.iseg rtc_data_const
	.align 0x2
	.global _month_lengths
_month_lengths:
; {
	.byte 0x0
; 	00,
	.byte 0x1f
	.byte 0x1c
	.byte 0x1f
; 	31, 28, 31,
	.byte 0x1e
	.byte 0x1f
	.byte 0x1e
; 	30, 31, 30,
	.byte 0x1f
	.byte 0x1f
	.byte 0x1e
; 	31, 31, 30,
	.byte 0x1f
	.byte 0x1e
; 	31, 30, 31
	.byte 0x1f
; month_lengths size 13
; };
; void set_rtc_sumcheck(void)
	.dbgseg dbg_syms
DBG3:
	.long 0x0
	.long DBG10
	.long _set_rtc_sumcheck
	.long 0x40
	.long 0x1020001
	.long DBG1
	.long DBG7-DBG8
	.long DBG9
	.long DBG6
	.long 0x0
	.pseg rtc_code
DBG8:
	.dbgseg dbg_syms
DBG1:
	.long 0x66622e
	.long 0x0
	.long DBG8
	.long 0x0
	.long 0x1650001
	.long 0x0
	.long 0x27
	.long 0x0
	.long DBG11
	.long 0x0
	.dbgseg dbg_line
	.align 0x2
DBG9:
	.long DBG3
	.long 0x0
	.long _set_rtc_sumcheck
	.long 0x1
	.long DBG13
	.long 0x2
	.long DBG14
	.long 0x3
	.long DBG15
	.long 0x4
	.pseg rtc_code
	.global _set_rtc_sumcheck
_set_rtc_sumcheck:
; ENTRY
DBG12:
; {
DBG13:
; 	rtc.sumcheck = ~(rtc.second + rtc.minute + rtc.hour + rtc.day + rtc.month + rtc.year);
DBG14:
	mov.b	&_rtc,r12
	add.b	&_rtc+0x1,r12
	add.b	&_rtc+0x2,r12
	add.b	&_rtc+0x3,r12
	add.b	&_rtc+0x5,r12
	add.b	&_rtc+0x6,r12
	inv.b	r12
	mov.b	r12,&_rtc+0x7
DBG16:
DBG15:
; EXIT
	ret
	.dbgseg dbg_syms
	.long 0x0
	.long DBG17
	.long 0x0
	.long 0x0
	.long 0x10002
	.long 0x0
	.long DBG18
	.long 0x2
	.long 0x0
	.long 0x10002
	.long 0x504e5f5f
	.long 0x534d5241
	.long 0x0
	.long 0x0
	.long 0x10002
	.long 0x66652e
	.long 0x0
	.long DBG16
	.long 0x0
	.long 0x1650001
	.long 0x0
	.long 0x2a
	.long 0x0
	.long 0x0
	.long 0x0
	.pseg rtc_code
DBG7:
	.dbgseg dbg_syms
	.long 0x0
	.long DBG10
	.long DBG7
	.long 0x0
	.long 0xff0001
; }
; int check_rtc_sumcheck(void)
DBG6:
	.long 0x0
	.long DBG23
	.long _check_rtc_sumcheck
	.long 0x44
	.long 0x1020001
	.long DBG11
	.long DBG20-DBG21
	.long DBG22
	.long DBG19
	.long 0x0
	.pseg rtc_code
DBG21:
	.dbgseg dbg_syms
DBG11:
	.long 0x66622e
	.long 0x0
	.long DBG21
	.long 0x0
	.long 0x1650001
	.long 0x0
	.long 0x2d
	.long 0x0
	.long DBG24
	.long 0x0
	.dbgseg dbg_line
DBG22:
	.long DBG6
	.long 0x0
	.long _check_rtc_sumcheck
	.long 0x1
	.long DBG26
	.long 0x2
	.long DBG27
	.long 0x3
	.long DBG28
	.long 0x4
	.pseg rtc_code
	.global _check_rtc_sumcheck
_check_rtc_sumcheck:
	push	r4
	push	r5
DBG27:
DBG26:
DBG25:
; ENTRY
; {
; 	return rtc.sumcheck == ((~(rtc.second + rtc.minute + rtc.hour + rtc.day + rtc.month + rtc.year
	mov.b	&_rtc+0x6,r5
	mov.b	&_rtc+0x5,r12
	mov.b	&_rtc+0x3,r13
	mov.b	&_rtc+0x2,r14
	mov.b	&_rtc+0x1,r15
	mov.b	&_rtc,r4
	add	r15,r4
	add	r14,r4
	add	r13,r4
	add	r12,r4
	add	r5,r4
	inv	r4
	and	#0xff,r4
	mov.b	&_rtc+0x7,r12
	cmp	r4,r12
	jeq	check_rtc_sumcheck_LL2
	mov	#0x0,r12
	jmp	check_rtc_sumcheck_LL3
check_rtc_sumcheck_LL2:
	mov	#0x1,r12
check_rtc_sumcheck_LL3:
	jmp	check_rtc_sumcheck_LL4
DBG28:
; )) & 0xFF);
check_rtc_sumcheck_LL4:
; EXIT
; .temp0 at stkloc 0 (0x0) size 4
DBG29:
	pop	r5
	pop	r4
	ret
	.dbgseg dbg_syms
	.long 0x0
	.long DBG17
	.long 0x4
	.long 0x0
	.long 0x10002
	.long 0x0
	.long DBG18
	.long 0x2
	.long 0x0
	.long 0x10002
	.long 0x504e5f5f
	.long 0x534d5241
	.long 0x0
	.long 0x0
	.long 0x10002
	.long 0x66652e
	.long 0x0
	.long DBG29
	.long 0x0
	.long 0x1650001
	.long 0x0
	.long 0x30
	.long 0x0
	.long 0x0
	.long 0x0
	.pseg rtc_code
DBG20:
	.dbgseg dbg_syms
	.long 0x0
	.long DBG23
	.long DBG20
	.long 0x0
	.long 0xff0001
; }
; int bump_rtc(void)
DBG19:
	.long 0x706d7562
	.long 0x6374725f
	.long _bump_rtc
	.long 0x44
	.long 0x1020001
	.long DBG24
	.long DBG31-DBG32
	.long DBG33
	.long DBG30
	.long 0x0
	.pseg rtc_code
DBG32:
	.dbgseg dbg_syms
DBG24:
	.long 0x66622e
	.long 0x0
	.long DBG32
	.long 0x0
	.long 0x1650001
	.long 0x0
	.long 0x35
	.long 0x0
	.long DBG34
	.long 0x0
	.dbgseg dbg_line
DBG33:
	.long DBG19
	.long 0x0
	.long _bump_rtc
	.long 0x1
	.long DBG36
	.long 0x2
	.long DBG37
	.long 0x5
	.long DBG38
	.long 0x6
	.long DBG39
	.long 0x7
	.long DBG40
	.long 0x8
	.long DBG41
	.long 0x9
	.long DBG42
	.long 0xa
	.long DBG43
	.long 0xb
	.long DBG44
	.long 0xc
	.long DBG45
	.long 0xd
	.long DBG46
	.long 0xe
	.long DBG47
	.long 0xf
	.long DBG48
	.long 0x10
	.long DBG49
	.long 0x11
	.long DBG50
	.long 0x12
	.long DBG51
	.long 0x13
	.long DBG52
	.long 0x14
	.long DBG53
	.long 0x15
	.long DBG54
	.long 0x16
	.long DBG55
	.long 0x17
	.long DBG56
	.long 0x18
	.long DBG57
	.long 0x1b
	.long DBG58
	.long 0x1c
	.long DBG59
	.long 0x1d
	.long DBG60
	.long 0x1e
	.long DBG61
	.long 0x1f
	.long DBG62
	.long 0x20
	.long DBG63
	.long 0x21
	.long DBG64
	.long 0x22
	.long DBG65
	.long 0x23
	.long DBG66
	.long 0x24
	.long DBG67
	.long 0x25
	.long DBG68
	.long 0x26
	.long DBG69
	.long 0x27
	.long DBG70
	.long 0x28
	.long DBG71
	.long 0x29
	.long DBG72
	.long 0x2a
	.long DBG73
	.long 0x2b
	.pseg rtc_code
	.global _bump_rtc
_bump_rtc:
; ENTRY
DBG35:
; {
DBG36:
; 	if (!check_rtc_sumcheck())
DBG37:
	call	#_check_rtc_sumcheck
	cmp	#0x0,r12
	jne	bump_rtc_L1
DBG38:
; 		return 0 ;
	mov	#0x0,r12
	jmp	bump_rtc_LL2
DBG39:
bump_rtc_L1:
;     if ( ++rtc.second < 60)
	mov.b	#0x3c,r12
	add.b	#0x1,&_rtc
	mov.b	&_rtc,r13
	cmp.b	r12,r13
	jc	bump_rtc_L2
DBG41:
DBG40:
;     {
;     	set_rtc_sumcheck();
	call	#_set_rtc_sumcheck
DBG42:
;     	return 1 ;
	mov	#0x1,r12
	jmp	bump_rtc_LL2
DBG44:
DBG43:
;     }
bump_rtc_L2:
;     rtc.second = 0;
	mov.b	#0x0,&_rtc
DBG45:
;     if ( ++rtc.minute < 60)
	add.b	#0x1,&_rtc+0x1
	mov.b	&_rtc+0x1,r13
	cmp.b	r12,r13
	jc	bump_rtc_L3
DBG47:
DBG46:
;     {
;     	set_rtc_sumcheck();
	call	#_set_rtc_sumcheck
DBG48:
; 		return 2 ;
	mov	#0x2,r12
	jmp	bump_rtc_LL2
DBG50:
DBG49:
;     }
bump_rtc_L3:
;     rtc.minute = 0;
	mov.b	#0x0,&_rtc+0x1
DBG51:
;     if ( ++rtc.hour < 24)
	add.b	#0x1,&_rtc+0x2
	mov.b	&_rtc+0x2,r12
	cmp.b	#0x18,r12
	jc	bump_rtc_L4
DBG53:
DBG52:
;     {
;     	set_rtc_sumcheck();
	call	#_set_rtc_sumcheck
DBG54:
; 		return 3 ;
	mov	#0x3,r12
	jmp	bump_rtc_LL2
DBG56:
DBG55:
;     }
bump_rtc_L4:
;     rtc.hour = 0;
	mov.b	#0x0,&_rtc+0x2
DBG57:
;     if ((rtc.month == 2  &&  (rtc.year & 3) == 0  &&  rtc.day < 29)
;     	||
	cmp.b	#0x2,&_rtc+0x5
	jne	bump_rtc_L7
	bit.b	#0x3,&_rtc+0x6
	jne	bump_rtc_L7
	cmp.b	#0x1d,&_rtc+0x3
	jnc	bump_rtc_L6
bump_rtc_L7:
	mov.b	&_rtc+0x5,r12
	cmp.b	_month_lengths(r12),&_rtc+0x3
	jc	bump_rtc_L5
bump_rtc_L6:
;     	rtc.day < month_lengths[rtc.month])
;     {
DBG58:
;         ++rtc.day;
DBG59:
	add.b	#0x1,&_rtc+0x3
DBG60:
;     	set_rtc_sumcheck();
	call	#_set_rtc_sumcheck
DBG61:
; 		return 4 ;
	mov	#0x4,r12
	jmp	bump_rtc_LL2
DBG63:
DBG62:
;  	}
bump_rtc_L5:
;     rtc.day = 1;
	mov.b	#0x1,&_rtc+0x3
DBG64:
;     if ( ++rtc.month <= 12)
	mov.b	#0xc,r13
	add.b	#0x1,&_rtc+0x5
	mov.b	&_rtc+0x5,r12
	cmp.b	r12,r13
	jnc	bump_rtc_L8
DBG66:
DBG65:
;     {
;     	set_rtc_sumcheck();
	call	#_set_rtc_sumcheck
DBG67:
;     	return 5 ;
	mov	#0x5,r12
	jmp	bump_rtc_LL2
DBG69:
DBG68:
;     }
bump_rtc_L8:
;     rtc.month = 1;
	mov.b	#0x1,&_rtc+0x5
DBG70:
;    	++rtc.year;
	add.b	#0x1,&_rtc+0x6
DBG71:
;     set_rtc_sumcheck();
	call	#_set_rtc_sumcheck
DBG72:
; 	return 6 ;
	mov	#0x6,r12
DBG73:
bump_rtc_LL2:
; EXIT
DBG74:
	ret
	.dbgseg dbg_syms
	.long 0x0
	.long DBG17
	.long 0x0
	.long 0x0
	.long 0x10002
	.long 0x0
	.long DBG18
	.long 0x2
	.long 0x0
	.long 0x10002
	.long 0x504e5f5f
	.long 0x534d5241
	.long 0x0
	.long 0x0
	.long 0x10002
	.long 0x66652e
	.long 0x0
	.long DBG74
	.long 0x0
	.long 0x1650001
	.long 0x0
	.long 0x5f
	.long 0x0
	.long 0x0
	.long 0x0
	.pseg rtc_code
DBG31:
	.dbgseg dbg_syms
	.long 0x706d7562
	.long 0x6374725f
	.long DBG31
	.long 0x0
	.long 0xff0001
; }
; int weekday(void)
DBG30:
	.long 0x6b656577
	.long 0x796164
	.long _weekday
	.long 0x44
	.long 0x1020001
	.long DBG34
	.long DBG76-DBG77
	.long DBG78
	.long DBG75
	.long 0x0
	.pseg rtc_code
DBG77:
	.dbgseg dbg_syms
DBG34:
	.long 0x66622e
	.long 0x0
	.long DBG77
	.long 0x0
	.long 0x1650001
	.long 0x0
	.long 0x64
	.long 0x0
	.long DBG79
	.long 0x0
	.dbgseg dbg_line
DBG78:
	.long DBG30
	.long 0x0
	.long _weekday
	.long 0x1
	.long DBG81
	.long 0x2
	.long DBG82
	.long 0x9
	.long DBG83
	.long 0xb
	.long DBG84
	.long 0xc
	.long DBG85
	.long 0xe
	.long DBG86
	.long 0xf
	.long DBG87
	.long 0x11
	.long DBG88
	.long 0x13
	.long DBG89
	.long 0x14
	.long DBG90
	.long 0x15
	.long DBG91
	.long 0x16
	.pseg rtc_code
	.global _weekday
_weekday:
; ENTRY
DBG80:
; i in reg  size 2
; days in reg  size 2

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