pllcfg.s

在S3C44b0上移植ucos并实现哲学家就餐问题的演示

;**************************************************************************
;NAME: PLLCFG.S
;copyright:wzz at Qingdao University 2008
;**************************************************************************
;Address define
;**************************************************************************
aPLLCON     EQU     0x01D80000;R/W, PLL configuration Register, 0x38080
aCLKCON     EQU     0x01D80004;R/W, Clock generator control Register, 0x7ff8
aCLKSLOW    EQU     0x01D80008;R/W, Slow clock control register, 0x9
aLOCKTIME   EQU     0x01D8000C;R/W, PLL lock time count register, 0xfff
;**************************************************************************
;系统时钟预定义
;-----------------------------------------------------------------------------

;M_DIV	EQU	0x48
;P_DIV	EQU	0x2
;S_DIV	EQU	0x1

M_DIV	EQU	0x34
P_DIV	EQU	0x3
S_DIV	EQU	0x1		

;**************************************************************************
;PLL configuration Register 
;aPLLCON	   	EQU	0x01d80000
;Reset Value 	 0x38080             
;-----------------------------------------------------------------------------
;Fin=6MHz,Fout=60MHz,m/p/s=0x48/2/1  72
;Fin=10MHz,Fout=60MHz,m/p/s=0x34/3/1  52
;fpllo=(m*Fin)/(p*2^s)
;m=M+8,p=P+2
cPLLCON		EQU	((M_DIV<<12)+(P_DIV<<4)+S_DIV)
;**************************************************************************
;CLOCK CONTROL REGISTER (CLKCON) 
;aCLKCON	    	EQU	0x01d80004
;Reset Value  0x7ff8              
;-----------------------------------------------------------------------------
CLK_IIS		EQU		(2_1<<14)
CLK_IIC		EQU		(2_1<<13)
CLK_ADC		EQU		(2_1<<12)
CLK_RTC		EQU		(2_1<<11)
CLK_GPIO	EQU		(2_1<<10)
CLK_UART1	EQU		(2_1<<9)
CLK_UART0	EQU		(2_1<<8)
CLK_BDMA01	EQU		(2_1<<7)
CLK_LCDC	EQU		(2_1<<6)
CLK_SIO		EQU		(2_1<<5)
CLK_ZDMA01	EQU		(2_1<<4)
CLK_PWM		EQU		(2_1<<3)
CLK_IDLE	EQU		(2_0<<2)
CLK_SIDLE	EQU		(2_0<<1)
CLK_STOP	EQU		(2_0<<0)
;-----------------------------------------------------------------------------
;All unit block CLK enable	
cCLKCON	   	EQU	0x7FF8
;cCLKCON	EQU		(CLK_IIS+CLK_IIC+CLK_ADC+CLK_RTC+CLK_GPIO+CLK_UART1+CLK_UART0+CLK_BDMA01+CLK_LCDC+CLK_SIO+CLK_ZDMA01+CLK_PWM+CLK_IDLE+CLK_SIDLE+CLK_STOP)
;******************************************************************************
;CLOCK SLOW CONTROL REGISTER (CLKSLOW)
;RESET 0x9 
;-----------------------------------------------------------------------------
PLL_OFF		EQU		(2_0<<5)	;0 : PLL is turned on. 
     							;PLL is turned on only when SLOW_BIT is 1. 
    							;After PLL stabilization time (minimum 150uS),  SLOW_BIT  may be cleared to 0. 
								;1 : PLL is turned off. 
     							;PLL is turned off only when SLOW_BIT is 1. 
SLOW_BIT	EQU		(2_0<<4)	;0 : Fout = Fpllo (PLL output) 
								;1: Fout = Fin / (2 x SLOW_VAL), (SLOW_VAL > 0
   								;Fout = Fin, (SLOW_VAL = 0) 
SLOW_VAL	EQU		0x9			;The divider value for the slow clock when SLOW_BIT is on.
;-----------------------------------------------------------------------------
cCLKSLOW	EQU		PLL_OFF+SLOW_BIT+SLOW_VAL
;******************************************************************************
;LOCK TIME COUNT REGISTER (LOCKTIME)
;aLOCKTIME  	EQU	0x01d8000c
;-----------------------------------------------------------------------------
; count = t_lock * Fin (t_lock=200us, Fin=4MHz) = 800
cLOCKTIME	EQU 	800
;******************************************************************************
 END