memcfg.s

在S3C44b0上移植ucos并实现哲学家就餐问题的演示

;**************************************************************************
;NAME: MEMCFG.s
;copyright:wzz at Qingdao University 2008
;**************************************************************************
;Address define
;**************************************************************************
aBWSCON     EQU     0x01C80000
aBANKCON0   EQU     0x01C80004
aBANKCON1   EQU     0x01C80008
aBANKCON2   EQU     0x01C8000C
aBANKCON3   EQU     0x01C80010
aBANKCON4   EQU     0x01C80014
aBANKCON5   EQU     0x01C80018
aBANKCON6   EQU     0x01C8001C
aBANKCON7   EQU     0x01C80020
aREFRESH    EQU     0x01C80024
aBANKSIZE   EQU     0x01C80028
aMRSRB6     EQU     0x01C8002C
aMRSRB7     EQU     0x01C80030
;**************************************************************************
;"DRAM","SDRAM"
                GBLS    BDRAMTYPE
BDRAMTYPE	SETS    "SDRAM"
;============================================================
;BWSCON
;ST7 WS7 DW7 ST6 WS6 DW6...ST1 WS1 DW1 DW0 ENDIAN

;ST
;This bit determines SRAM for using UB/LB for bank X:
;0 = Not using UB/LB ( Pin[14:11] is dedicated nWBE[3:0] ) 
;1 = Using UB/LB ( Pin[14:11] is dedicated nBE[3:0] )

;WS
;This bit determines WAIT status for bank X:
;0 = WAIT disable, 1 = WAIT enable

;DW
;These two bits determine data bus width for bank X:
;00 = 8-bit 01 = 16-bit, 10 = 32-bit

;BUSWIDTH=16
cBWSCON16   EQU   0x11111012	;Bank0=16bit BootRom(AT29LV160DB) :0x0
;                  ||||||--	 Bank1=low 8bit D12               :0x4
;                  |||||---	 Bank2=8bit  NAND-Flash(KM29U128T):0x2
;                  ||||----	 Bank3=16bit Expend               :0x6
;                  |||-----	 Bank4=16bit Expend		  :0x8
;                  ||------	 Bank5=16bit ISA                  :0xA
;                  |-------   Bank6=16bit SDRAM                :0xc
;                  --------   Bank7=16bit NoUsed
;BUSWIDTH=32
;BWSCON_cfg EQU  0x22222220	;Bank0=OM[1:0], Bank1~Bank7=32bit
;**********MEMORY CONTROL PARAMETERS*******************************
;When MCLK=66MHz,1clk=0.0152us=15.2ns
;Bank 0 parameter for Monitor Rom
;============================================================


;nGCS0-nGCS5
;Tacs [14:13] Address set-up before nGCSn
;Tcos [12:11] Chip selection set-up nOE
;Tacc [10:8]  Access cycle
;Toch [7:6]   Chip selection hold on nOE
;Tcah [5:4]   Address holding time after nGCSn
;Tpac [3:2]   Page mode access cycle @ Page mode
;PMC  [1:0]   Page mode configuration
;BANK0 "SDRAM"
B0_Tacs EQU 0x0;1clk
B0_Tcos EQU 0x0;1clk
B0_Tacc EQU 0x7;14clk
B0_Toch EQU 0x0;1clk
B0_Tcah EQU 0x0;1clk
B0_Tpac EQU 0x0;1clk
B0_PMC  EQU 0x0;normal

;BANK1
B1_Tacs EQU 0x3;1clk
B1_Tcos EQU 0x3;1clk
B1_Tacc EQU 0x7;6clk
B1_Toch EQU 0x3;1clk
B1_Tcah EQU 0x3;1clk
B1_Tpac EQU 0x3;1clk
B1_PMC  EQU 0x0;normal

;BANK2
B2_Tacs EQU 0x3;1clk
B2_Tcos EQU 0x3;1clk
B2_Tacc EQU 0x7;6clk
B2_Toch EQU 0x3;1clk
B2_Tcah EQU 0x3;1clk
B2_Tpac EQU 0x3;1clk
B2_PMC  EQU 0x0;normal

;BANK3
B3_Tacs EQU 0x3;1clk
B3_Tcos EQU 0x3;1clk
B3_Tacc EQU 0x7;6clk
B3_Toch EQU 0x3;1clk
B3_Tcah EQU 0x3;1clk
B3_Tpac EQU 0x3;1clk
B3_PMC  EQU 0x0;normal

;BANK4
B4_Tacs EQU 0x3;1clk
B4_Tcos EQU 0x3;1clk
B4_Tacc EQU 0x7;6clk
B4_Toch EQU 0x3;1clk
B4_Tcah EQU 0x3;1clk
B4_Tpac EQU 0x3;1clk
B4_PMC  EQU 0x0;normal

;BANK5
B5_Tacs EQU 0x3;1clk
B5_Tcos EQU 0x3;1clk
B5_Tacc EQU 0x7;6clk
B5_Toch EQU 0x3;1clk
B5_Tcah EQU 0x3;1clk
B5_Tpac EQU 0x0;1clk
B5_PMC  EQU 0x0;normal

;BANK6&7
;MT [16:15] These two bits determines the memmory type
;Memory Type=Rom or SRAM MT=00
;Tacs [14:13] Address set-up before nGCSn
;Tcos [12:11] Chip selection set-up nOE
;Tacc [10:8]  Access cycle
;Toch [7:6]   Chip selection hold on nOE
;Tcah [5:4]   Address holding time after nGCSn
;Tpac [3:2]   Page mode access cycle @ Page mode
;PMC  [1:0]   Page mode configuration
;Memory Type=FP DRAM MT=01
;EDO DRAM [MT=10]
;Trcd [5:4] RAS to CAS delay
;Tcas [3]   CAS pulse width
;Tcp  [2]   CAS pre-charge
;CAN  [1:0] Column address number
;
;Bank 6(if SROM) parameter
B6_Tacs		EQU	0x3	;4clk
B6_Tcos		EQU	0x3	;4clk
B6_Tacc		EQU	0x7	;14clk
B6_Tcoh		EQU	0x3	;4clk
B6_Tah		EQU	0x3	;4clk
B6_Tacp		EQU	0x3	;6clk
B6_PMC		EQU	0x0	;normal(1data)

;Bank 7(if SROM) parameter
B7_Tacs		EQU	0x3	;4clk
B7_Tcos		EQU	0x3	;4clk
B7_Tacc		EQU	0x7	;14clk
B7_Tcoh		EQU	0x3	;4clk
B7_Tah		EQU	0x3	;4clk
B7_Tacp		EQU	0x3	;6clk
B7_PMC		EQU	0x0	;normal(1data)

;Bank 6 parameter
	[ BDRAMTYPE="DRAM"	;MT=01(FP DRAM) or 10(EDO DRAM) 
B6_MT		EQU	0x2	;EDO DRAM
B6_Trcd		EQU	0x0	;1clk
B6_Tcas		EQU	0x0	;1clk
B6_Tcp		EQU	0x0	;1clk
B6_CAN		EQU	0x2	;10bit
	| ;"SDRAM"		;MT=11(SDRAM)
B6_MT		EQU	0x3	;SDRAM
B6_Trcd		EQU	0x0	;2clk
B6_SCAN		EQU	0x0	;8bit
	]

;Bank 7 parameter
	[ BDRAMTYPE="DRAM"	;MT=01(FP DRAM) or 10(EDO DRAM) 
B7_MT		EQU	0x2	;EDO DRAM
B7_Trcd		EQU	0x0	;2clk
B7_Tcas		EQU	0x0	;2clk
B7_Tcp		EQU	0x0	;2clk
B7_CAN		EQU	0x2	;10bit
	| ;"SDRAM"		;MT=11(SDRAM)
B7_MT		EQU	0x3	;SDRAM
B7_Trcd		EQU	0x0	;2clk
B7_SCAN		EQU	0x0	;8bit
	]

;REFRESH CONTROL REGISTER
;REFEN [23] DRAM/SDRAM Refresh Enable
;TREFMD [22] DRAM/SDRAM Refresh Mode
;REFRESH parameter
REFEN		EQU	0x1	;Refresh enable
TREFMD		EQU	0x0	;CBR(CAS before RAS)/Auto refresh
Trp		EQU	0x0	;2clk
Trc		EQU	0x0	;4clk
Tchr		EQU	0x2	;3clk
REFCNT		EQU	1425     ;1019	;period=15.6us, MCLK=66Mhz

;************************************************
 
 END