wsfrcdef.h

在S3C44b0上移植ucos并实现哲学家就餐问题的演示

/**************************************************************************
NAME:WSFRCDEF.H
copyright:wzz at Qingdao University  2008
**************************************************************************/
//#include "WOPTIONS.h"
#ifndef __WSFRCDEF_H__
#define __WSFRCDEF_H__

#ifdef __cplusplus
extern "C" {
#endif
//****************************************************************************
//CPU
//===========================================================================
#define SYSC_CM0	(0x0<<2)	//No CACHE
#define SYSC_CM4	(0x1<<2)	//4K CACHE
#define SYSC_CM8	(0x3<<2)	//8K CACHE
//---------------------------------------------------------------------------
#define SYSC_DA		(0x0<<5)	//DATA	ABORT controls
#define SYSC_RSE	(0x0<<4)	//Enable read stall options
#define SYSC_WE		(0x1<<3)	//write_buf_on
#define SYSC_CM		SYSC_CM8	//8k CACHE
#define SYSC_SE		(0x0<<0)	//Enable stall options
#define crSYSCFG	(SYSC_DA+SYSC_RSE+SYSC_WE+SYSC_CM+SYSC_SE)
//----------------------------------------------------------------------------
#define bcCHACHEBIT	!(0x3<<2)	//CLAER cache bits
#define bsCHACHE0KB	SYSC_CM0	//0K CACHE
//-----------------------------------------------------------------------------

//*****************************************************************************
//ports init
//-----------------------------------------------------------------------------
	//CAUTION:Follow the configuration order for setting the ports. 
	// 1) setting value 
	 // 2) setting control register 
	 // 3) configure pull-up resistor.  

	//16bit data bus configuration  
	
	// PORT A GROUP
	/*  BIT 9		8		7		6		5		4		3		2		1		0            */
	/*  ADDR24	ADDR23	ADDR22	ADDR21	ADDR20	ADDR19	ADDR18	ADDR17	ADDR16	ADDR0   */	      
	/*  1,			1,		1,          1,           1,      1,                 1,          1,          1,           1           */
//#define		cPCONA  0x3ff;
//	// PORT B GROUP
//	/*	BIT 10	9		8		7		6		5		4		3		2		1		0*/
//	/*    /CS5	/CS4	/CS3	/CS2	/CS1	nWBE3	nWBE2	/SRAS	/SCAS	SCLK	SCKE*/
//	/*	rtl8019	(Reserve)(Reserve)FLASH	D12 		Out		Out		Sdram	Sdram	Sdram	Sdram*/
//	/*      1,        1,		1,		1,		1,		0,		0,		1,		1,		1,		1*/
//#define		cPDATB  0x7ff;
//#define		cPCONB  0x7cf;
//    
//	//PORT C GROUP
//	//BUSWIDTH=16*/
//	/*  PC    15		14		13		12		11		10		9		8                       */
//	/*          O		O		RXD1	TXD1	O		O		O		O*/
//	/*          Nand-CE	UDA-CE	Uart1	Uart1	NandCLE	NandALE	L3DATA	L3CLK*/
//	/*          01		01		11		11		01		01		01		01		*/
//
//	/*  PC	7		6		5		4		3		2		1		0*/
//	/*		O		O		O		I		IISCLK	IISDI	IISDO	IISLRCK*/
//	/*		VD4		VD5		VD6		VD7		[		for UDA1341			]*/
//	/*		11		11		11		11		11		11		11		11*/
//#define		cPDATC  0x3fff;	//All IO is high
//#define		cPCONC  0x5f55ffff;	
//#define		cPUPC   0x3000;	//PULL UP RESISTOR should be enabled to I/O
//
//	//PORT D GROUP for LCD
//	/*BIT 7	6	5		4		3		2		1		0*/
//	/*      VF	VM	VLINE	VCLK	VD3		VD2		VD1		VD0*/
//	/*	  10	10	10		10		10		10		10		10*/
//#define		cPDATD 0xff;
//#define		cPCOND 0xaaaa;
//#define		cPUPD  0x0;
//	
//	//PORT E GROUP
//	/*  Bit	 	8		7		6		5		4		3		2		1		0	*/
//	/*		CODECLK	TOUT4	TOUT3	TOUT2	TOUT1	TOUT0	RXD0	TXD0	SMRB(I)	*/
//	/*			10		10		10		10		10		10		10		10		00	*/
//#define		cPDATE  0x1ff;
//#define		cPCONE  0x2aaa8;
//#define		cPUPE   0x106;
//
//	//PORT F GROUP
//	/*  Bit	8		7		6		5		4		3		2		1	      0*/
//	/*		SIOCLK	SIORxD	7843CS	SIOTxD	[Input(DMA)	]	Output	IICSDA	IICSCL*/
//	/*		011		011		001		011		00		00		01		10     	10*/
//
//#define		cPDATF  0x1fb;	//GPF2=0
//#define		cPCONF  0x1B2C1A;	//0x9241A;
//#define		cPUPF   0x3;
//
//	//PORT G GROUP
//	/*BIT	7		6		5		4		3		2		1		0*/
//	/*		INT7		INT6		INT5		INT4		INT3		INT2		INT1		INT0*/
//	/*		11		11		00		00		11		11		11		11*/
//	//						~~~~~~~~input for bios
//#define		cPDATG  0xff;
//#define		cPCONG  0xf0ff;
//#define		cPUPG   0x0;	//should be enabled  
//
//
//
//#define		cSPUCR 0x7;  //D15-D0 pull-up disable
//
//	/*定义非Cache区*/
//#define		cNCACHBE0 (((unsigned int)Non_Cache_End>>12)<<16)|(Non_Cache_Start>>12); 
//	/*所有的外部硬件中断为低电平触发*/
//#define		cEXTINT 0x0;
//******************************************************************************************
#define crUBRDIV0 ((int)(MCLK/16./115200 + 0.5) -1 );
//******************************************************************************************
//UART LINE CONTROL REGISTER 0
//;-----------------------------------------------------------------------------------------
#define ULCON0_RED 	 (0x0<<6)   	//0 Normal mode
			            			//1 Infra-Red Tx/Rx mode
#define ULCON0_PM  	 (0x000<3)		//0xx No parity
									//100 Odd
									//101 Even
									//110
									//111
#define ULCON0_STOP	 (0x0<2) 	//0 One stop bit per frame
									//1 Two stop bit per frame
#define ULCON0_LEN	 (0x3<<0)	//00 5 bits
//							;01 6 bits
//							;10 7 bits
//							;11 8 bits
//;-----------------------------------------------------------------------------------------
#define crULCON0  (ULCON0_RED|ULCON0_PM|ULCON0_STOP|ULCON0_LEN)
//#define crULCON0 0x03
//;****************************************************************************************
//UART CONTROL REGISTER 0
//;***************************************************************************************
#define UCON0_TX	(0x0<<9)		//;0 Pulse 1 Level
#define	UCON0_RX	(0x0<<8)		//;0 Pulse 1 Level
#define	UCON0_TEN	(0x0<<7)		//;Rx time out
#define	UCON0_INT	(0x0<<6)		//;genertate an interrupt
#define	UCON0_LOOP	(0x0<<5)		//0 = Normal operation 1 = Loop-back mode
#define	UCON0_BRK	(0x0<<4)		//0 = Normal transmit 1 = Send break signal
#define	UCON0_TM	(0x2<<2)		//;Transmit Mode
#define	UCON0_RM	(0x1<<0)		//;Receive Mode
//;---------------------------------------------------------------------------------------
//#define crUCON0 	(UCON0_TX|UCON0_RX|UCON0_TEN|UCON0_INT|UCON0_LOOP|UCON0_BRK|UCON0_TM|UCON0_RM)
#define crUCON0 0x05
//;*****************************************************************************************

//UART FIFO CONTROL REGISTER
//;*****************************************************************************************
//aUFCON0		EQU 0x01D00008
//;-----------------------------------------------------------------------------------------
#define UFCON0_TX	 (0x0<<7)	//;Trigger level of transmit FIFO
#define UFCON0_RX	 (0x0<<5)	//;Trigger level of receive  FIFO
#define UFCON0_TRe	 (0x0<<3)	//;This bit is auto-cleared after reseting FIFO
#define UFCON0_RRe	 (0x0<<2)	//;This bit is auto-cleared after resetting FIFO
								//0 = Normal 1= Rx FIFO reset
#define UFCON0_EN	 (0x0<<0)	//0 = FIFO disable 1 = FIFO mode
//;----------------------------------------------------------------------------------------
#define	crUFCON0_DIS	0x0	
#define	crUFCON0_NMAL	(UFCON0_TX|UFCON0_RX|UFCON0_TRe|UFCON0_RRe|UFCON0_EN)
//;-------------------------------------------------------------------------------------------
//;*****************************************************************************************

#ifdef __cplusplus
}
#endif
#endif