📄 intcfg.s
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;**************************************************************************
;NAME: INTCFG.s
;copyright:wzz at Qingdao University 2008
;**************************************************************************
;Interrupt Control
;**************************************************************************
;Address define
;--------------------------------------------------------------------------
aINTCON EQU 0x01E00000
aINTPND EQU 0x01E00004
aINTMOD EQU 0x01E00008
aINTMSK EQU 0x01E0000C
aI_PSLV EQU 0x01E00010
aI_PMST EQU 0x01E00014
aI_CSLV EQU 0x01E00018
aI_CMST EQU 0x01E0001C
aI_ISPR EQU 0x01E00020
aI_ISPC EQU 0x01E00024
aF_ISPC EQU 0x01E0003C
aEXTINT EQU 0x01D20050 ;
aEXTINTPND EQU 0x01D20054
;**************************************************************************
;INTERRUPT CONTROL REGISTER
;**************************************************************************
;aINTCON EQU 0x01E00000
;--------------------------------------------------------------------------
INTCON_V EQU (2_0<<2) ;This bit disables/enables vector mode for IRQ
;0 = Vectored interrupt mode
;1 = Non-vectored interrupt mode
INTCON_I EQU (2_0<<1) ;This bit enables IRQ interrupt request line to CPU
;0 = IRQ interrupt enable
;1 = Reserved
;Note : Before using the IRQ interrupt this bit must be cleared.
INTCON_F EQU (2_0<<0) ;This bit enables FIQ interrupt request line to CPU
;0 = FIQ interrupt enable (Not allowed vectored interrupt mode)
;1 = Reserved
;Note : Before using the FIQ interrupt this bit must be cleared.
;--------------------------------------------------------------------------
cINTCON EQU INTCON_V+INTCON_I+INTCON_F
;**************************************************************************
;INTERRUPT PENDING REGISTER (INTPND) Initial State 0
;**************************************************************************
;INTERRUPT MODE REGISTER (INTMOD)
;26 Interrupt source
;0 = IRQ mode 1 = FIQ mode
;**************************************************************************
;aINTMOD EQU 0x01E00008
;--------------------------------------------------------------------------
IMOD_EINT0 EQU (2_0<<25)
IMOD_EINT1 EQU (2_0<<24)
IMOD_EINT2 EQU (2_0<<23)
IMOD_EINT3 EQU (2_0<<22)
IMOD_EINT4567 EQU (2_0<<21)
IMOD_TICK EQU (2_0<<20)
IMOD_ZDMA0 EQU (2_0<<19)
IMOD_ZDMA1 EQU (2_0<<18)
IMOD_BDMA0 EQU (2_0<<17)
IMOD_BDMA1 EQU (2_0<<16)
IMOD_WDT EQU (2_0<<15)
IMOD_UERR01 EQU (2_0<<14)
IMOD_TIMER0 EQU (2_0<<13)
IMOD_TIMER1 EQU (2_0<<12)
IMOD_TIMER2 EQU (2_0<<11)
IMOD_TIMER3 EQU (2_0<<10)
IMOD_TIMER4 EQU (2_0<<9)
IMOD_TIMER5 EQU (2_0<<8)
IMOD_URXD0 EQU (2_0<<7)
IMOD_URXD1 EQU (2_0<<6)
IMOD_IIC EQU (2_0<<5)
IMOD_SIO EQU (2_0<<4)
IMOD_UTXD0 EQU (2_0<<3)
IMOD_UTXD1 EQU (2_0<<2)
IMOD_RTC EQU (2_0<<1)
IMOD_ADC EQU (2_0<<0)
;--------------------------------------------------------------------------
cINTMOD EQU IMOD_EINT0+IMOD_EINT1+IMOD_EINT2+IMOD_EINT3+IMOD_EINT4567+IMOD_TICK+IMOD_ZDMA0+IMOD_ZDMA1+IMOD_BDMA0+IMOD_BDMA1+IMOD_WDT+IMOD_UERR01+IMOD_TIMER0+IMOD_TIMER1+IMOD_TIMER2+IMOD_TIMER3+IMOD_TIMER4+IMOD_TIMER5+IMOD_URXD0+IMOD_URXD1+IMOD_IIC+IMOD_SIO+IMOD_UTXD0+IMOD_UTXD1+IMOD_RTC+IMOD_ADC
;**************************************************************************
;INTERRUPT MASK REGISTER (INTMSK)
;**************************************************************************
;aINTMSK EQU 0x01E0000C
;--------------------------------------------------------------------------
;Global 26 others are the same as above
;0 = Interrupt service is available
;1 = Interrupt service is masked
;--------------------------------------------------------------------------
IMSK_GBL EQU (2_0<<26)
IMSK_EINT0 EQU (2_0<<25)
IMSK_EINT1 EQU (2_0<<24)
IMSK_EINT2 EQU (2_0<<23)
IMSK_EINT3 EQU (2_0<<22)
IMSK_EINT4567 EQU (2_0<<21)
IMSK_TICK EQU (2_0<<20)
IMSK_ZDMA0 EQU (2_0<<19)
IMSK_ZDMA1 EQU (2_0<<18)
IMSK_BDMA0 EQU (2_0<<17)
IMSK_BDMA1 EQU (2_0<<16)
IMSK_WDT EQU (2_0<<15)
IMSK_UERR01 EQU (2_0<<14)
IMSK_TIMER0 EQU (2_0<<13)
IMSK_TIMER1 EQU (2_0<<12)
IMSK_TIMER2 EQU (2_0<<11)
IMSK_TIMER3 EQU (2_0<<10)
IMSK_TIMER4 EQU (2_0<<9)
IMSK_TIMER5 EQU (2_0<<8)
IMSK_URXD0 EQU (2_0<<7)
IMSK_URXD1 EQU (2_0<<6)
IMSK_IIC EQU (2_0<<5)
IMSK_SIO EQU (2_0<<4)
IMSK_UTXD0 EQU (2_0<<3)
IMSK_UTXD1 EQU (2_0<<2)
IMSK_RTC EQU (2_0<<1)
IMSK_ADC EQU (2_0<<0)
;--------------------------------------------------------------------------
cINTMSK EQU IMSK_GBL+IMSK_EINT0+IMSK_EINT1+IMSK_EINT2+IMSK_EINT3+IMSK_EINT4567+IMSK_TICK+IMSK_ZDMA0+IMSK_ZDMA1+IMSK_BDMA0+IMSK_BDMA1+IMSK_WDT+IMSK_UERR01+IMSK_TIMER0+IMSK_TIMER1+IMSK_TIMER2+IMSK_TIMER3+IMSK_TIMER4+IMSK_TIMER5+IMSK_URXD0+IMSK_URXD1+IMSK_IIC+IMSK_SIO+IMSK_UTXD0+IMSK_UTXD1+IMSK_RTC+IMSK_ADC
cINTMSK_Reset EQU 0x07ffffff
;**************************************************************************
;IRQ PRIORITY OF SLAVE REGISTER (I_PSLV)
;I_PSLV determines the interrupt priorities among the 4 interrupt sources of each slave group.
;00: 1st 01: 2nd 10: 3rd 11: 4th
;--------------------------------------------------------------------------
;PSLAVE@mGA
;----------------------------------------
IPS_EINT0 EQU (2_00<<30)
IPS_EINT1 EQU (2_01<<28)
IPS_EINT2 EQU (2_10<<26)
IPS_EINT3 EQU (2_11<<24)
;----------------------------------------
;PSLAVE@mGB
;----------------------------------------
IPS_ZDMA0 EQU (2_00<<22)
IPS_ZDMA1 EQU (2_01<<20)
IPS_BDMA0 EQU (2_10<<18)
IPS_BDMA1 EQU (2_11<<16)
;----------------------------------------
;PSLAVE@mGC
;----------------------------------------
IPS_TIMER0 EQU (2_00<<14)
IPS_TIMER1 EQU (2_01<<12)
IPS_TIMER2 EQU (2_10<<10)
IPS_TIMER3 EQU (2_11<<8)
;----------------------------------------
;PSLAVE@mGD
;----------------------------------------
IPS_URXD0 EQU (2_00<<6)
IPS_URXD1 EQU (2_01<<4)
IPS_IIC EQU (2_10<<2)
IPS_SIO EQU (2_11<<0)
;--------------------------------------------------------------------------
cI_PSLV EQU IPS_EINT0+IPS_EINT1+IPS_EINT2+IPS_EINT3+IPS_ZDMA0+IPS_ZDMA1+IPS_BDMA0+IPS_BDMA1+IPS_TIMER0+IPS_TIMER1+IPS_TIMER2+IPS_TIMER3+IPS_URXD0+IPS_URXD1+IPS_IIC+IPS_SIO
;**************************************************************************
;IRQ PRIORITY OF MASTER REGISTER (I_PMST)
;--------------------------------------------------------------------------
IPM_M EQU (2_1<<12)
;0 = round robin 1 = fix mode
;----------------------------------------
;FxSLV[A:D]
;0 = round robin 1 = fix mode
;----------------------------------------
IPM_FxA EQU (2_1<<11)
IPM_FxB EQU (2_1<<10)
IPM_FxC EQU (2_1<<9)
IPM_FxD EQU (2_1<<8)
;----------------------------------------
;PMAST
;00: 1st 01: 2nd 10: 3rd 11: 4th
;----------------------------------------
IPM_A EQU (2_00<<6)
IPM_B EQU (2_01<<4)
IPM_C EQU (2_10<<2)
IPM_D EQU (2_11<<0)
;--------------------------------------------------------------------------
cI_PMST EQU IPM_M+IPM_FxA+IPM_FxB+IPM_FxC+IPM_FxD+IPM_A+IPM_B+IPM_C+IPM_D
;**************************************************************************
;ISPC
;IRQ interrupt service pending clear register
;--------------------------------------------------------------------------
;F_ISPC
;FIQ interrupt service pending clear register
;**************************************************************************
;**************************************************************************
;--------------------------------------------------------------------------
;Register Address R/W Description Reset Value
;INTCON 0x01E00000 R/W Interrupt control Register 0x7
;INTPND 0x01E00004 R Indicates the interrupt request status.
; 0 = The interrupt has not been requested,
; 1 = The interrupt source has asserted the interrupt request 0x0000000
;INTMOD 0x01E00008 R/W Interrupt mode Register
; 0 = IRQ mode 1 = FIQ mode 0x0000000
;INTMSK 0x01E0000C R/W Determines which interrupt source is masked.
; The masked interrupt source will not be serviced.
; 0 = Interrupt service is available
; 1 = Interrupt service is masked 0x07ffffff
;I_PSLV 0x01E00010 R/W IRQ priority of slave register 0x1B1B1B1B
;I_PMST 0x01E00014 R/W IRQ priority of master register 0x00001f1B
;I_CSLV 0x01E00018 R Current IRQ priority of slave register 0x1B1B1B1B
;I_CMST 0x01E0001C R Current IRQ priority of master register 0x0000xx1B
;I_ISPR 0x01E00020 R IRQ interrupt service pending register
; (Only one service bit can be set) 0x00000000
;I_ISPC 0x01E00024 W IRQ interrupt service clear register
; (Whatever to be set, INTPND will be cleared automatically) Undef.
;F_ISPC 0x01E0003C W FIQ interrupt service pending clear register Undef.
;EXTINT 0x01D20050 R/W External Interrupt control Register 0x000000
;EXTINTPND 0x01D20054 R/W External interrupt pending Register 0x00
;--------------------------------------------------------------------------
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