📄 dianti.vhi
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-- VHDL Instantiation Created from source file dianti.vhd -- 20:02:55 01/10/2008
--
-- Notes:
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit
COMPONENT dianti
PORT(
A : IN std_logic;
B : IN std_logic;
floor1 : IN std_logic;
floor2 : IN std_logic;
floor3 : IN std_logic;
floor4 : IN std_logic;
floor5 : IN std_logic;
floor6 : IN std_logic;
clk : IN std_logic;
reset : IN std_logic;
position : OUT std_logic_vector(3 downto 0);
go_up : OUT std_logic;
go_down : OUT std_logic;
forbid : OUT std_logic
);
END COMPONENT;
Inst_dianti: dianti PORT MAP(
position => ,
go_up => ,
go_down => ,
forbid => ,
A => ,
B => ,
floor1 => ,
floor2 => ,
floor3 => ,
floor4 => ,
floor5 => ,
floor6 => ,
clk => ,
reset =>
);
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