dianti.syr

六层电梯

 4-bit 4-to-1 multiplexer          : 3

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <dianti> ...
WARNING:Xst:1710 - FF/Latch  <position_3> (without init value) has a constant value of 0 in block <dianti>.
Loading device for application Rf_Device from file 'v100.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block dianti, actual ratio is 12.
FlipFlop position_2 has been replicated 2 time(s)
FlipFlop request_stop_floor_0 has been replicated 1 time(s)
FlipFlop request_up_floor_0 has been replicated 1 time(s)
FlipFlop state_FFd1 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : dianti.ngr
Top Level Output File Name         : dianti
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 17

Macro Statistics :
# Registers                        : 24
#      1-bit register              : 23
#      6-bit register              : 1
# Multiplexers                     : 10
#      1-bit 4-to-1 multiplexer    : 7
#      4-bit 4-to-1 multiplexer    : 3
# Adders/Subtractors               : 1
#      6-bit adder                 : 1

Cell Usage :
# BELS                             : 304
#      GND                         : 1
#      INV                         : 2
#      LUT1                        : 5
#      LUT2                        : 14
#      LUT2_D                      : 6
#      LUT2_L                      : 4
#      LUT3                        : 40
#      LUT3_D                      : 13
#      LUT3_L                      : 7
#      LUT4                        : 112
#      LUT4_D                      : 20
#      LUT4_L                      : 63
#      MUXCY                       : 5
#      MUXF5                       : 6
#      VCC                         : 1
#      XORCY                       : 5
# FlipFlops/Latches                : 35
#      FDC                         : 13
#      FDCE                        : 18
#      FDE                         : 3
#      FDP                         : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 16
#      IBUF                        : 9
#      OBUF                        : 7
=========================================================================

Device utilization summary:
---------------------------

Selected Device : v100pq240-4 

 Number of Slices:                     150  out of   1200    12%  
 Number of Slice Flip Flops:            35  out of   2400     1%  
 Number of 4 input LUTs:               284  out of   2400    11%  
 Number of bonded IOBs:                 17  out of    170    10%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 35    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 16.069ns (Maximum Frequency: 62.232MHz)
   Minimum input arrival time before clock: 9.738ns
   Maximum output required time after clock: 11.424ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 16.069ns (frequency: 62.232MHz)
  Total number of paths / destination ports: 3045 / 52
-------------------------------------------------------------------------
Delay:               16.069ns (Levels of Logic = 5)
  Source:            t_3 (FF)
  Destination:       t_5 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: t_3 to t_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             18   1.372   3.300  t_3 (t_3)
     LUT4:I1->O           18   0.738   3.300  Ker96 (N96)
     LUT4:I0->O            3   0.738   1.628  _n0140 (_n0140)
     LUT4_D:I1->LO         1   0.738   0.100  Ker114 (N1782)
     LUT2:I1->O            5   0.738   1.914  Ker1139_SW2 (N1635)
     LUT4_L:I3->LO         1   0.738   0.000  _n0065<2>1 (_n0065<2>)
     FDC:D                     0.765          t_2
    ----------------------------------------
    Total                     16.069ns (5.827ns logic, 10.242ns route)
                                       (36.3% logic, 63.7% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 69 / 26
-------------------------------------------------------------------------
Offset:              9.738ns (Levels of Logic = 3)
  Source:            A (PAD)
  Destination:       request_up_floor_1 (FF)
  Destination Clock: clk rising

  Data Path: A to request_up_floor_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            18   0.989   3.300  A_IBUF (A_IBUF)
     LUT2:I0->O            4   0.738   1.760  _n0297_SW0 (N141)
     LUT4:I3->O            1   0.738   1.265  _n0297 (_n0297)
     FDCE:CE                   0.948          request_up_floor_1
    ----------------------------------------
    Total                      9.738ns (3.413ns logic, 6.325ns route)
                                       (35.0% logic, 65.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 6 / 6
-------------------------------------------------------------------------
Offset:              11.424ns (Levels of Logic = 1)
  Source:            position_1 (FF)
  Destination:       position<1> (PAD)
  Source Clock:      clk rising

  Data Path: position_1 to position<1>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             36   1.372   4.400  position_1 (position_1)
     OBUF:I->O                 5.652          position_1_OBUF (position<1>)
    ----------------------------------------
    Total                     11.424ns (7.024ns logic, 4.400ns route)
                                       (61.5% logic, 38.5% route)

=========================================================================
CPU : 21.22 / 21.52 s | Elapsed : 21.00 / 21.00 s
 
--> 

Total memory usage is 116788 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    1 (   0 filtered)