dianti.twr

六层电梯

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Release 7.1i Trace H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

C:/Xilinx/bin/nt/trce.exe -ise d:\df\df.ise -intstyle ise -e 3 -l 3 -s 4 -xml
dianti dianti.ncd -o dianti.twr dianti.pcf


Design file:              dianti.ncd
Physical constraint file: dianti.pcf
Device,speed:             xcv100,-4 (FINAL 1.123 2005-01-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
A           |    8.743(R)|   -1.353(R)|clk_BUFGP         |   0.000|
B           |    9.736(R)|   -1.424(R)|clk_BUFGP         |   0.000|
floor1      |    5.169(R)|   -0.904(R)|clk_BUFGP         |   0.000|
floor2      |    6.708(R)|   -1.429(R)|clk_BUFGP         |   0.000|
floor3      |    7.557(R)|   -0.992(R)|clk_BUFGP         |   0.000|
floor4      |    7.094(R)|   -0.676(R)|clk_BUFGP         |   0.000|
floor5      |    6.716(R)|   -0.433(R)|clk_BUFGP         |   0.000|
floor6      |    4.426(R)|   -0.676(R)|clk_BUFGP         |   0.000|
reset       |    6.608(R)|   -1.897(R)|clk_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
forbid      |    7.884(R)|clk_BUFGP         |   0.000|
go_down     |    7.926(R)|clk_BUFGP         |   0.000|
go_up       |    7.926(R)|clk_BUFGP         |   0.000|
position<0> |   14.313(R)|clk_BUFGP         |   0.000|
position<1> |   13.300(R)|clk_BUFGP         |   0.000|
position<2> |   13.318(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |   19.168|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Thu Jan 10 20:19:37 2008
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Peak Memory Usage: 69 MB