test_dianti.v

来自「六层电梯」· Verilog 代码 · 共 42 行

`timescale 1ns/100ps
module test;
reg floor1,floor2,floor3,floor4,floor5,floor6,clk,A,B,reset;
wire [3:0]position;
wire go_up,go_down,forbid;

always #5 clk=~clk;

initial
begin
clk=1;floor1=0;floor2=0;floor3=0;floor4=0;floor5=0;floor6=0;reset=1;A=0;B=0;
#1 reset=0;
#1 reset=1;

#20 A=1;B=0;floor3=1;
#10 A=0;B=0;floor3=0;
#40 A=0;B=0;floor5=1;
#20 A=0;B=0;floor5=0;
#2000 A=0;B=0;floor1=1;
#20 A=0;B=0;floor1=0;
#40 A=0;B=0;floor2=1;
#20 A=0;B=0;floor2=0;
#20 A=1;B=0;floor4=1;
#10 A=0;B=0;floor4=0;
#1500 A=0;B=0;floor1=1;
#10 A=0;B=0;floor1=0;
#1300 A=1;B=0;floor3=1;
#10 A=0;B=0;floor3=0;
#10 A=0;B=0;floor6=1;
#10 A=0;B=0;floor6=0;
#300 A=0;B=0;floor1=1;
#10 A=0;B=0;floor1=0;

#1000 A=1;B=0;floor4=1;
#10 A=0;B=0;floor4=0;


#1000 $stop;
end
dianti ti (position,go_up,go_down,forbid,A,B,floor1,floor2,floor3,floor4,floor5,floor6,clk,reset);

endmodule