📄 start_v2.lst
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642 ; : = :
643 ; 3 = 3 clock cycles
644 ;
645 ; <o>WRPHF1: Phase F write clock cycles (TCONCS1.13 .. TCONCS1.14) <0-3>
0003 646 _WRPHF1 EQU 3 ; 0 = 0 clock cycles
647 ; : = :
648 ; 3 = 3 clock cycles
A166 MACRO ASSEMBLER START_V2 09/02/2008 15:32:01 PAGE 11
649 ;</h> </e>
650 ;
651 ;<e>Configure External Bus Behaviour for CS2 Area
652 ; =============================================
653 ;
654 ; --- Set CONFIG_CS2 = 1 to initialize the ADDRSEL2/FCONCS2/TCONCS2 registers
655 $SET (CONFIG_CS2 = 0)
656 ;
657 ; <h>Definitions for Address Select register ADDRSEL2
658 ; ===================================================
659 ; <o> CS2 Start Address <0x0-0xFFFFFF:0x1000>
00200000 660 _ADDR2 EQU 0x200000 ; Set CS2# Start Address (default 100000H)
661
662 ; <o> CS2 Size in KB
663 ; <4=> 4KB <8=> 8KB <16=> 16KB <32=> 32KB
664 ; <64=> 64KB <128=> 128KB <256=> 256KB <512=> 512KB
665 ; <1024=> 1024KB <2048=> 2048KB <4096=> 4096KB <8192=> 8192KB
00100000 666 _SIZE2 EQU 1024*KB ; Set CS2# Size (default 1024*KB = 1*MB)
667 ; possible values for _SIZE2 are:
668 ; 4*KB (gives RGSZ2 = 0)
669 ; 8*KB (gives RGSZ2 = 1)
670 ; 16*KB (gives RGSZ2 = 2)
671 ; 32*KB (gives RGSZ2 = 3)
672 ; 64*KB (gives RGSZ2 = 4)
673 ; 128*KB (gives RGSZ2 = 5)
674 ; 256*KB (gives RGSZ2 = 6)
675 ; 512*KB (gives RGSZ2 = 7)
676 ; 1024*KB or 1*MB (gives RGSZ2 = 8)
677 ; 2048*KB or 2*MB (gives RGSZ2 = 9)
678 ; 4096*KB or 4*MB (gives RGSZ2 = 10)
679 ; 8192*KB or 8*MB (gives RGSZ2 = 11)
680 ; (RGSZ2 = 12 .. 15 reserved)
681 ;</h>
682 ;
683 ; <h>Definitions for Function Configuration Register FCONCS2
684 ; =======================================================
685 ;
686 ; <q> ENCS2: Enable Chip Select (FCONCS2.0)
0001 687 _ENCS2 EQU 1 ; 0 = Chip Select 0 disabled
688 ; 1 = Chip Select 0 enabled
689 ;
690 ; <q> RDYEN2: Ready Enable (FCONCS2.1)
0000 691 _RDYEN2 EQU 0 ; 0 = Access time controlled by TCONCS2.PHE1
692 ; 1 = Access time cont. by TCONCS2.PHE1 and READY signal
693 ;
694 ; <o> RDYMOD2: Ready Mode (FCONCS2.2)
695 ; <0=> Asynchronous <1=> Synchronous
0000 696 _RDYMOD2 EQU 0 ; 0 = Asynchronous READY
697 ; 1 = Synchronous READY
698 ;
699 ; <o> BTYP2: Bus Type Selection (FCONCS2.4 .. FCONCS2.5)
700 ; <0=> 8-bit Demultiplexed Bus <1=> 8-bit Multiplexed Bus
701 ; <2=> 16-bit Demultiplexed Bus <3=> 16-bit Multiplexed Bus
0002 702 _BTYP2 EQU 2 ; 0 = 8 bit Demultiplexed bus
703 ; 1 = 8 bit Multiplexed bus
704 ; 2 = 16 bit Demultiplexed bus
705 ; 3 = 16 bit Multiplexed bus
706 ;</h>
707 ;
708 ; <h>TCONCS2: Definitions for the Timing Configuration register
709 ; ==========================================================
710 ;
711 ; <o>PHA2: Phase A clock cycle (TCONCS2.0 .. TCONCS2.1) <0-3>
0000 712 _PHA2 EQU 0 ; 0 = 0 clock cycles
713 ; : = :
714 ; 3 = 3 clock cycles
A166 MACRO ASSEMBLER START_V2 09/02/2008 15:32:01 PAGE 12
715 ;
716 ; <o>PHB2: Phase B clock cycle (TCONCS2.2) <1-2> <#-1>
0000 717 _PHB2 EQU 0 ; 0 = 1 clock cycle
718 ; 1 = 2 clock cycles
719 ;
720 ; <o>PHC2: Phase C clock cycle (TCONCS2.3 .. TCONCS2.4) <0-3>
0000 721 _PHC2 EQU 0 ; 0 = 0 clock cycles
722 ; : = :
723 ; 3 = 3 clock cycles
724 ;
725 ; <o>PHD2: Phase D clock cycle (TCONCS2.5) <0-1>
0000 726 _PHD2 EQU 0 ; 0 = 0 clock cycles
727 ; 1 = 1 clock cycle
728 ;
729 ; <o> PHE2: Phase E clock cycle (TCONCS2.6 .. TCONCS2.10) <1-32> <#-1>
0008 730 _PHE2 EQU 8 ; 0 = 1 clock cycle
731 ; : = :
732 ; 31 = 32 clock cycles
733 ;
734 ; <o>RDPHF2: Phase F read clock cycle (TCONCS2.11 .. TCONCS2.12) <0-3>
0000 735 _RDPHF2 EQU 0 ; 0 = 0 clock cycles
736 ; : = :
737 ; 3 = 3 clock cycles
738 ;
739 ; <o>WRPHF2: Phase F write clock cycle (TCONCS2.13 .. TCONCS2.14) <0-3>
0003 740 _WRPHF2 EQU 3 ; 0 = 0 clock cycles
741 ; : = :
742 ; 3 = 3 clock cycles
743 ;</h> </e>
744 ;
745 ;<e>Configure External Bus Behaviour for CS3 Area
746 ; =============================================
747 ;
748 ; --- Set CONFIG_CS3 = 1 to initialize the ADDRSEL3/FCONCS3/TCONCS3 registers
749 $SET (CONFIG_CS3 = 0)
750 ;
751 ; <h>Definitions for Address Select register ADDRSEL3
752 ; ===================================================
753 ; <o> CS3 Start Address <0x0-0xFFFFFF:0x1000>
00300000 754 _ADDR3 EQU 0x300000 ; Set CS3# Start Address (default 100000H)
755
756 ; <o> CS2 Size in KB
757 ; <4=> 4KB <8=> 8KB <16=> 16KB <32=> 32KB
758 ; <64=> 64KB <128=> 128KB <256=> 256KB <512=> 512KB
759 ; <1024=> 1024KB <2048=> 2048KB <4096=> 4096KB <8192=> 8192KB
00100000 760 _SIZE3 EQU 1024*KB ; Set CS3# Size (default 1024*KB = 1*MB)
761 ; possible values for _SIZE3 are:
762 ; 4*KB (gives RGSZ3 = 0)
763 ; 8*KB (gives RGSZ3 = 1)
764 ; 16*KB (gives RGSZ3 = 2)
765 ; 32*KB (gives RGSZ3 = 3)
766 ; 64*KB (gives RGSZ3 = 4)
767 ; 128*KB (gives RGSZ3 = 5)
768 ; 256*KB (gives RGSZ3 = 6)
769 ; 512*KB (gives RGSZ3 = 7)
770 ; 1024*KB or 1*MB (gives RGSZ3 = 8)
771 ; 2048*KB or 2*MB (gives RGSZ3 = 9)
772 ; 4096*KB or 4*MB (gives RGSZ3 = 10)
773 ; 8192*KB or 8*MB (gives RGSZ3 = 11)
774 ; (RGSZ3 = 12 .. 15 reserved)
775 ;</h>
776 ;
777 ; <h>Definitions for Function Configuration Register FCONCS3
778 ; =======================================================
779 ;
780 ; <q> ENCS3: Enable Chip Select (FCONCS3.0)
A166 MACRO ASSEMBLER START_V2 09/02/2008 15:32:01 PAGE 13
0001 781 _ENCS3 EQU 1 ; 0 = Chip Select 0 disabled
782 ; 1 = Chip Select 0 enabled
783 ;
784 ; <q> RDYEN3: Ready Enable (FCONCS3.1)
0000 785 _RDYEN3 EQU 0 ; 0 = Access time controlled by TCONCS3.PHE1
786 ; 1 = Access time cont. by TCONCS3.PHE1 and READY signal
787 ;
788 ; <o> RDYMOD3: Ready Mode (FCONCS3.2)
789 ; <0=> Asynchronous <1=> Synchronous
0000 790 _RDYMOD3 EQU 0 ; 0 = Asynchronous READY
791 ; 1 = Synchronous READY
792 ;
793 ; <o> BTYP3 Bus Type Selection (FCONCS3.4 .. FCONCS3.5)
794 ; <0=> 8-bit Demultiplexed Bus <1=> 8-bit Multiplexed Bus
795 ; <2=> 16-bit Demultiplexed Bus <3=> 16-bit Multiplexed Bus
0002 796 _BTYP3 EQU 2 ; 0 = 8 bit Demultiplexed bus
797 ; 1 = 8 bit Multiplexed bus
798 ; 2 = 16 bit Demultiplexed bus
799 ; 3 = 16 bit Multiplexed bus
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