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📄 start_v2.lst

📁 利用xc167单片机上的双口can
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                          478     ; <o> APDIS: Address Port Pins Disable (EBCMOD1.0 .. EBCMOD0.4) <0-31:31>
 0000                     479     _APDIS     EQU    0     ; 0  = Address port PORT1 used as address bus
                          480                             ; 1 - 30 = reserved
                          481                             ; 31 = Address bus disabled (PORT1 used as GPIO)
                          482     ;
                          483     ; <q> DHPDIS: Data High Port Pins Disable (EBCMOD1.6)
 0000                     484     _DHPDIS    EQU    0     ; 0 = Data bus pins 15-8 of PORT0 enabled
                          485                             ; 1 = Data bus pins 15-8 disabled (used as GPIO)
                          486     ;
                          487     ;</h></e>
                          488     ;
                          489     ; <e>Configure External Bus Behaviour for CS0 area
                          490     ; ================================================
                          491     ;
                          492     ; --- Set CONFIG_CS0 = 1 to initialize the FCONCS0/TCONCS0 registers
                          493     $SET (CONFIG_CS0 = 0)
                          494     ;
                          495     ; <h>Definitions for Function Configuration Register FCONCS0
                          496     ; =======================================================
                          497     ;
                          498     ; <q> ENCS0: Enable Chip Select (FCONCS0.0)
 0001                     499     _ENCS0     EQU    1     ; 0 = Chip Select 0 disabled
                          500                             ; 1 = Chip Select 0 enabled
                          501     ;
                          502     ; <q> RDYEN0: Ready Enable (FCONCS0.1)
 0000                     503     _RDYEN0    EQU    0     ; 0 = Access time controlled by TCONCS0.PHE0
                          504                             ; 1 = Access time cont. by TCONCS0.PHE0 and READY signal
                          505     ;
                          506     ; <o> RDYMOD0: Ready Mode (FCONCS0.2) 
                          507     ; <0=> Asynchronous  <1=> Synchronous
 0000                     508     _RDYMOD0   EQU    0     ; 0 = Asynchronous READY
                          509                             ; 1 = Synchronous READY
                          510     ;
                          511     ; <o> BTYP0: Bus Type Selection (FCONCS0.4 .. FCONCS0.5)
                          512     ; <0=> 8-bit Demultiplexed Bus  <1=> 8-bit Multiplexed Bus
                          513     ; <2=> 16-bit Demultiplexed Bus <3=> 16-bit Multiplexed Bus
 0002                     514     _BTYP0     EQU    2     ; 0 = 8 bit Demultiplexed bus
                          515                             ; 1 = 8 bit Multiplexed bus
                          516                             ; 2 = 16 bit Demultiplexed bus
A166 MACRO ASSEMBLER  START_V2                                                            09/02/2008 15:32:01 PAGE     9

                          517                             ; 3 = 16 bit Multiplexed bus
                          518     ; </h>
                          519     ;
                          520     ; <h> TCONCS0: Definitions for the Timing Configuration register 
                          521     ; ==========================================================
                          522     ;
                          523     ; <o> PHA0: Phase A clock cycles (TCONCS0.0 .. TCONCS0.1) <0-3>
 0003                     524     _PHA0       EQU    3    ; 0 = 0 clock cycles
                          525                             ; : = : 
                          526                             ; 3 = 3 clock cycles
                          527     ;
                          528     ; <o> PHB0: Phase B clock cycles (TCONCS0.2) <1-2> <#-1>
 0000                     529     _PHB0       EQU    0    ; 0 = 1 clock cycle
                          530                             ; 1 = 2 clock cycles
                          531     ;
                          532     ; <o> PHC0: Phase C clock cycles (TCONCS0.3 .. TCONCS0.4) <0-3>
 0000                     533     _PHC0       EQU    0    ; 0 = 0 clock cycles
                          534                             ; : = :
                          535                             ; 3 = 3 clock cycles
                          536     ;
                          537     ; <o> PHD0: Phase D clock cycle (TCONCS0.5) <0-1>
 0000                     538     _PHD0       EQU    0    ; 0 = 0 clock cycles
                          539                             ; 1 = 1 clock cycle
                          540     ;
                          541     ; <o> PHE0: Phase E clock cycles (TCONCS0.6 .. TCONCS0.10) <1-32> <#-1>
 0008                     542     _PHE0       EQU    8    ; 0 = 1 clock cycle
                          543                             ; : = :
                          544                             ; 31 = 32 clock cycles
                          545     ;
                          546     ; <o> RDPHF0: Phase F read clock cycles (TCONCS0.11 .. TCONCS0.12) <0-3>
 0000                     547     _RDPHF0     EQU    0    ; 0 = 0 clock cycles
                          548                             ; : = :
                          549                             ; 3 = 3 clock cycles
                          550     ;
                          551     ; <o> WRPHF0: Phase F write clock cycles (TCONCS0.13 .. TCONCS0.14) <0-3>
 0003                     552     _WRPHF0     EQU    3    ; 0 = 0 clock cycles
                          553                             ; : = :
                          554                             ; 3 = 3 clock cycles
                          555     ;</h> </e>
                          556     ;
                          557     ;<e>Configure External Bus Behaviour for CS1 Area
                          558     ;   =============================================
                          559     ;
                          560     ; --- Set CONFIG_CS1 = 1 to initialize the ADDRSEL1/FCONCS1/TCONCS1 registers
                          561     $SET (CONFIG_CS1 = 1)
                          562     ;
                          563     ; <h>Definitions for Address Select register ADDRSEL1
                          564     ; ===================================================
                          565     ; <o> CS1 Start Address   <0x0-0xFFFFFF:0x1000>
 00400000                 566     _ADDR1      EQU 0x400000     ; Set CS1# Start Address (default 100000H)
                          567     
                          568     ; <o> CS1 Size in KB      
                          569     ; <4=>    4KB      <8=>    8KB      <16=>   16KB     <32=>   32KB   
                          570     ; <64=>   64KB     <128=>  128KB    <256=>  256KB    <512=>  512KB
                          571     ; <1024=> 1024KB   <2048=> 2048KB   <4096=> 4096KB   <8192=> 8192KB
 00080000                 572     _SIZE1      EQU 512*KB         ; Set CS1# Size (default 1024*KB = 1*MB)
                          573                                  ; possible values for _SIZE1 are:
                          574                                  ;    4*KB            (gives RGSZ1 = 0)
                          575                                  ;    8*KB            (gives RGSZ1 = 1)
                          576                                  ;   16*KB            (gives RGSZ1 = 2)
                          577                                  ;   32*KB            (gives RGSZ1 = 3)
                          578                                  ;   64*KB            (gives RGSZ1 = 4)
                          579                                  ;  128*KB            (gives RGSZ1 = 5)
                          580                                  ;  256*KB            (gives RGSZ1 = 6)
                          581                                  ;  512*KB            (gives RGSZ1 = 7)
                          582                                  ; 1024*KB  or  1*MB  (gives RGSZ1 = 8)
A166 MACRO ASSEMBLER  START_V2                                                            09/02/2008 15:32:01 PAGE    10

                          583                                  ; 2048*KB  or  2*MB  (gives RGSZ1 = 9)
                          584                                  ; 4096*KB  or  4*MB  (gives RGSZ1 = 10)
                          585                                  ; 8192*KB  or  8*MB  (gives RGSZ1 = 11)
                          586                                  ;                    (RGSZ1 = 12 .. 15 reserved)
                          587     ;</h>
                          588     ;
                          589     ; <h>Definitions for Function Configuration Register FCONCS1
                          590     ; =======================================================
                          591     ;
                          592     ; <q> ENCS1: Enable Chip Select (FCONCS1.0)
 0001                     593     _ENCS1     EQU    1     ; 0 = Chip Select 0 disabled
                          594                             ; 1 = Chip Select 0 enabled
                          595     ;
                          596     ; <q> RDYEN1: Ready Enable (FCONCS1.1)
 0000                     597     _RDYEN1    EQU    0     ; 0 = Access time controlled by TCONCS1.PHE1
                          598                             ; 1 = Access time cont. by TCONCS1.PHE1 and READY signal
                          599     ;
                          600     ; <o> RDYMOD1: Ready Mode (FCONCS1.2)
                          601     ; <0=> Asynchronous  <1=> Synchronous
 0000                     602     _RDYMOD1   EQU    0     ; 0 = Asynchronous READY
                          603                             ; 1 = Synchronous READY
                          604     ;
                          605     ; <o> BTYP1: Bus Type Selection (FCONCS1.4 .. FCONCS1.5)
                          606     ; <0=> 8-bit Demultiplexed Bus  <1=> 8-bit Multiplexed Bus
                          607     ; <2=> 16-bit Demultiplexed Bus <3=> 16-bit Multiplexed Bus
 0002                     608     _BTYP1     EQU    2     ; 0 = 8 bit Demultiplexed bus
                          609                             ; 1 = 8 bit Multiplexed bus
                          610                             ; 2 = 16 bit Demultiplexed bus
                          611                             ; 3 = 16 bit Multiplexed bus
                          612     ;</h>
                          613     ;
                          614     ; <h>TCONCS1: Definitions for the Timing Configuration register 
                          615     ; ==========================================================
                          616     ;
                          617     ; <o>PHA1: Phase A clock cycles (TCONCS1.0 .. TCONCS1.1) <0-3>
 0003                     618     _PHA1       EQU    3    ; 0 = 0 clock cycles
                          619                             ; : = : 
                          620                             ; 3 = 3 clock cycles
                          621     ;
                          622     ; <o>PHB1: Phase B clock cycles (TCONCS1.2) <1-2> <#-1>
 0000                     623     _PHB1       EQU    0    ; 0 = 1 clock cycle
                          624                             ; 1 = 2 clock cycles
                          625     ;
                          626     ; <o>PHC1: Phase C clock cycles (TCONCS1.3 .. TCONCS1.4) <0-3>
 0000                     627     _PHC1       EQU    0    ; 0 = 0 clock cycles
                          628                             ; : = :
                          629                             ; 3 = 3 clock cycles
                          630     ;
                          631     ; <o>PHD1: Phase D clock cycles (TCONCS1.5) <0-1>
 0000                     632     _PHD1       EQU    0    ; 0 = 0 clock cycles
                          633                             ; 1 = 1 clock cycle
                          634     ;
                          635     ; <o> PHE1: Phase E clock cycles (TCONCS1.6 .. TCONCS1.10) <1-32> <#-1>
 0008                     636     _PHE1       EQU    8    ; 0 = 1 clock cycle
                          637                             ; : = :
                          638                             ; 31 = 32 clock cycles
                          639     ;
                          640     ; <o>RDPHF1: Phase F read clock cycles (TCONCS1.11 .. TCONCS1.12) <0-3>
 0000                     641     _RDPHF1     EQU    0    ; 0 = 0 clock cycles

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