📄 start_v2.lst
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320 ;
321 ; INIT_PLLCON: Init PLLCON register
322 ; --- Set INIT_PLLCON = 0 to initilize the PLLCON register
A166 MACRO ASSEMBLER START_V2 09/02/2008 15:32:01 PAGE 6
323 $SET (INIT_PLLCON = 1)
324 ;
325 ; <o> PLLODIV: PLL Output Devider (PLLCON.0 .. PLLCON.3) <0-14>
0003 326 _PLLODIV EQU 3 ; 0 .. 14 Fpll = Fvco / (PLLODIV+1)
327 ; 15 = reserved
328 ;
329 ; <o> PLLIDIV: PLL Input Devider (PLLCON.4 .. PLLCON.5) <0-3>
330 ; <i> Fin = Fosc / (PLLIDIV+1)
0000 331 _PLLIDIV EQU 0 ; 0 .. 3 Fin = Fosc / (PLLIDIV+1)
332 ;
333 ; <o> PLLVB: PLL VCO Band Select (PLLCON.6 .. PLLCON.7)
334 ; <0=> Ouput:100-150MHz / Base:20-80MHz <1=> Ouput:150-200MHz / Base:40-130MHz
335 ; <2=> Ouput:200-250MHz / Base:60-180MHz <3=> (250...300 MHz) Reserved
0001 336 _PLLVB EQU 1 ; ValueVCO output frequency Base frequency
337 ; 0 = 100...150 MHz 20...80 MHz
338 ; 1 = 150...200 MHz 40...130 MHz
339 ; 2 = 200...250 MHz [def.] 60...180 MHz
340 ; 3 = (250...300 MHz) Reserved
341 ;
342 ; <o> PLLMUL: PLL Multiplication Factor (PLLCON.8 .. PLLCON.12) <7-31>
343 ; <i> Fvco = Fin * (PLLMUL+1)
0013 344 _PLLMUL EQU 19 ; 7 .. 31 Fvco = Fin * (PLLMUL+1)
345 ; 0 .. 6 = reserved
346 ;
347 ; <o> PLLCTRL: PLL Operation Control (PLLCON.13 .. PLLCON.14)
348 ; <0=> Bypass PLL clock mult., the VCO is off <1=> Bypass PLL clock mult., the VCO i
s running
349 ; <2=> VCO clock used, input clock switched off <3=> VCO clock used, input clock conne
cted
0003 350 _PLLCTRL EQU 3 ; 0 = Bypass PLL clock mult., the VCO is off
351 ; 1 = Bypass PLL clock mult., the VCO is running
352 ; 2 = VCO clock used, input clock switched off
353 ; 3 = VCO clock used, input clock connected
354 ;
355 ; <o> PLLWRI: PLLCON Write Ignore Flag (PLLCON.15)
356 ; <0=> Register PLLCON may be written <1=> Write cycles to register PLLCON are ignore
d
0000 357 _PLLWRI EQU 0 ; 0 = Register PLLCON may be written
358 ; 1 = Write cycles to register PLLCON are ignored
359 ;</e>
360 ;
361 ; <e> Definitions for Watchdog Timer Control Register WDTCON
362 ; ======================================================
363 ;
364 ; --- Set WATCHDOG = 0 to enable the Hardware watchdog and initilize the WDTCON regist
er
365 $SET (WATCHDOG = 0) ; 0 = Disabled Hardware watchdog
366 ;
367 ; <o> WDTIN: Watchdog Timer Input Frequency Select (WDTCON.0 .. WDTCON.1)
368 ; <0=> Peripheral Frequency divided by 2 <1=> Peripheral Frequency divided by 128
369 ; <2=> Peripheral Frequency divided by 4 <3=> Peripheral Frequency divided by 256
0001 370 _WDTIN EQU 1 ; 0 = frequency f_peripheral / 2 (CPU default)
371 ; 1 = frequency f_peripheral / 128 (recommended for START_V2)
372 ; 2 = frequency f_peripheral / 4
373 ; 3 = frequency f_peripheral / 256
374 ;
375 ; <o> WDTREL: Watchdog Timer Reload Value (WDTCON8 .. WDTCON15) <0-255>
376 ; <i> High byte of WDT (counts up, overflow gives Watchdog reset)
0000 377 _WDTREL EQU 0
378 ;
379 ;</e>
380 ; <e> Definitions for Frequency Output Signal FOCON
381 ; =================================================
382 ;
383 ; INIT_FOCON: Init FOCON register
384 ; --- Set INIT_FOCON = 0 to initilize the FOCON register
A166 MACRO ASSEMBLER START_V2 09/02/2008 15:32:01 PAGE 7
385 $SET (INIT_FOCON = 0)
386 ;
387 ; <o> CLKEN: CLKOUT Enable (FOCON.7)
388 ; <0=> P3.15 is IO <1=> P3.15 is CLKOUT
0000 389 _CLKEN EQU 0 ; 0 = P3.15 is IO pin when _FOUT is 0
390 ; 1 = P3.15 outputs signal CLKOUT
391 ;
392 ; <o> FORV: Frequency Output Reload Value (FOCON.8 .. FOCON.13) <0-63>
393 ; <i> Is copied to FOCNT upon each underflow of FOCNT
0000 394 _FORV EQU 0
395 ;
396 ; <o> FOSS: Frequency Output Signal Select (FOCON.14)
397 ; <0=> Output of Toggle Latch <1=> Output of Reload Counter
0000 398 _FOSS EQU 0 ; 0 = Output of the toggle latch; 0.5 duty cycle
399 ; 1 = Output of reload counter; duty cycle depends on FORV
400 ;
401 ; <o> FOEN: Frequency Output Enable (FOCON.15)
402 ; <0=> P3.15 is IO <1=> P3.15 outputs f_OUT
0000 403 _FOEN EQU 0 ; 0 = P3.15 is IO pin when _CLKEN is 0
404 ; 1 = P3.15 outputs f_OUT when _CLKEN is 0
405 ;</e>
406 ;
407 ;<h> External Bus Configuration
408 ;
409 ; <e> Configure External Bus (EBC) Behaviour
410 ; ==========================================
411 ;
412 ; --- Set CONFIG_EBC = 0 to initialize the EBCMOD0/EBCMOD1 registers
413 $SET (CONFIG_EBC = 1) ; 0 = EBCMOD0/EBCMOD1 are set during reset according the
414 ; of configuration bus (typical Port0) values.
415 ; 1 = the following external bus configuration values
416 ; are written to EBCMOD and BUSACT0
417 ;
418 ; <h>Definitions for EBC Mode 0 register EBCMOD0
419 ; ===========================================
420 ;
421 ; <o> SAPEN: Segment Address Pins Enabled (EBCMOD0.0 .. EBCMOD0.3) <0-8>
422 ; <i> Number of active Address Lines (A16-A23)
0004 423 _SAPEN EQU 4 ; 0 = No segment address pins enabled
424 ; 1 = One (A16) segment address pin enabled
425 ; : = :
426 ; 8 = Eight (A16 .. A23) address pins enabled
427 ; 9 - 15 = reserved
428 ;
429 ; <o> CSPEN: CSx Pins Enabled (EBCMOD0.4 .. EBCMOD0.7) <0-8>
430 ; <i> Number of active ChipSelect pins
0003 431 _CSPEN EQU 3 ; 0 = No CS pins enabled
432 ; 1 = One CS (CS0) pin enabled
433 ; : = :
434 ; 8 = Eight CS (CS0 .. CS7) pins enabled
435 ; 9 - 15 = reserved
436 ; Note: the number of available CS pins depends on the chip used
437 ;
438 ; <q> ARBEN: Enable Bus Arbitration Pins (EBCMOD0.8)
0000 439 _ARBEN EQU 0 ; 0 = HOLD, HLDA and BREQ pins are tristate or act as GPIO
440 ; 1 = HOLD, HLDA and BREQ pins act normally
441 ;
442 ; <o> SLAVE: SLAVE mode enable (EBCMOD0.9)
443 ; <0=> Master Mode <1=> Slave Mode
0000 444 _SLAVE EQU 0 ; 0 = Bus arbiter acts in master mode
445 ; 1 = Bus arbiter acts in slave mode
446 ;
447 ; <q> EBCDIS: Disable EBC pins (EBCMOD0.10)
0000 448 _EBCDIS EQU 0 ; 0 = EBC is using the pins for external bus
449 ; 1 = EBC off (pins to be used as GPIO if implemented)
450 ;
A166 MACRO ASSEMBLER START_V2 09/02/2008 15:32:01 PAGE 8
451 ; <o> WRCFG: Configuration for pins WR/WRL and BHE/WRH (EBCMOD0.11)
452 ; <0=> WR and BHE <1=> WRL and WRH
0000 453 _WRCFG EQU 0 ; 0 = Pins act as WR and BHE
454 ; 1 = Pins act as WRL and WRH
455 ;
456 ; <q> BYTDIS: Disable BHE pin (EBCMOD0.12)
0000 457 _BYTDIS EQU 0 ; 0 = BHE enabled
458 ; 1 = BHE disabled (GPIO function if implemented)
459 ;
460 ; <q> ALEDIS: Disable ALE pin (EBCMOD0.13)
0000 461 _ALEDIS EQU 0 ; 0 = ALE pin enabled
462 ; 1 = ALE pin disabled (GPIO function if implemented)
463 ;
464 ; <q> RDYDIS: Disable READY pin (EBCMOD0.14)
0000 465 _RDYDIS EQU 0 ; 0 = READY enabled
466 ; 1 = READY disabled (GPIO function if implemented)
467 ;
468 ; <o> RDYPOL: READY pin polarity (EBCMOD0.15)
469 ; <0=> Active Low <1=> Active High
0000 470 _RDYPOL EQU 0 ; 0 = READY pin is active low
471 ; 1 = READY pin is active high
472 ;
473 ;</h>
474 ;
475 ; <h>Definitions for EBC Mode 1 register EBCMOD1
476 ; ===========================================
477 ;
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