📄 start_v2.lst
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0001 156 _RETST EQU 1 ; 0 = Return Stack disabled
157 ; 1 = Return Stack enabled
158 ;
159 ; <q> OVRUN: Allow Pipeline Bubble Overrun (CPUCON2.4)
0001 160 _OVRUN EQU 1 ; 0 = Overrun of Pipeline Bubbles not allowed
161 ; 1 = Overrun of Pipeline Bubbles allowed
162 ;
163 ; <q> ZSC: Enable Zero Cycle Jump Cache (CPUCON2.5)
0001 164 _ZSC EQU 1 ; 0 = Zero Cycle Jump Cache disabled
165 ; 1 = Zero Cycle Jump Cache enabled
166 ;
167 ; <q> STEN: Enable Stall Instruction (CPUCON2.6)
0000 168 _STEN EQU 0 ; 0 = Stall instruction disabled
169 ; 1 = Stall instruction enabled
170 ;
171 ; <q> EIOIAEN: Early IO Injection Acknowledge guaranteed
0001 172 _EIOIAEN EQU 1 ; 0 = Injection ack. by destructive read not guaranteed
173 ; ; 1 = Injection ack. by destructive read guaranteed
174 ;
175 ; <q> BYPF: Enable Fetch Bypass Control (CPUCON2.8)
0001 176 _BYPF EQU 1 ; 0 = Bypass Path from Fetch to Decode disabled
177 ; 1 = Bypass Path from Fetch to Decode enabled
178 ;
179 ; <q> BYPPF: Enable Prefecth Bypass Control (CPUCON2.9)
0001 180 _BYPPF EQU 1 ; 0 = Bypass Path from Prefetch to Decode disabled
181 ; 1 = Bypass Path from Prefetch to Decode enabled
182 ;
183 ; <o> FIFOFED: FIFO Fill Configuration (CPUCON2.10 .. CPUCON2.11)
184 ; <0=> FIFO disabled <1=> 1 instruction
185 ; <2=> 2 instructions <3=> 3 instructions
0003 186 _FIFOFED EQU 3 ; 0 = FIFO disabled
187 ; 1 = FIFO filled with up to 1 instruction per cycle
188 ; 2 = FIFO filled with up to 2 instructions per cycle
189 ; 3 = FIFO filled with up to 3 instructions per cycle
190 ;
A166 MACRO ASSEMBLER START_V2 09/02/2008 15:32:01 PAGE 4
191 ;<o> FIFODEPTH: FIFO Depth Configuration (CPUCON2.12 .. CPUCON2.15) <0-8>
0008 192 _FIFODEPTH EQU 8 ; 0 = No FIFO entries (No FIFO)
193 ; 1 = 1 FIFO entry
194 ; ...
195 ; 8 = 8 FIFO entries
196 ; 9 - 15 = reserved
197 ;</e>
198 ;</h>
199 ; <h> Peripheral Configuration
200 ; ============================
201 ;
202 ; <e> Definitions for System Configuration Register SYSCON1
203 ; =========================================================
204 ;
205 ; INIT_SYSCON1: Init SYSCON1 register
206 ; --- Set INIT_SYSCON1 = 1 to initilize the SYSCON1 register
207 $SET (INIT_SYSCON1 = 0)
208 ;
209 ; <q> SLEEPCON: Sleep Mode Configuration (SYSCON1.0 .. SYSCON1.1)
210 ; <0=> IDLE mode upon IDLE instr. <1=> SLEEP mode upon IDLE instr.
0000 211 _SLEEPCON EQU 0 ; 0 = Normal IDLE mode entered upone IDLE instruction
212 ; 1 = SLEEP mode entered upon IDLE instruction
213 ; 2 - 3 = reserved
214 ;
215 ; <q> PDCFG: Port Driver Configuration (SYSCON1.2 .. SYSCON1.3)
216 ; <0=>Port drivers are always ON <1=>Port drivers are off in IDLE/Sleep mode
217 ; <2=>Port drivers are off in Powerdown mode
0000 218 _PDCFG EQU 0 ; 0 = Port drivers are always ON (default)
219 ; 1 = Port drivers are off in IDLE or Sleep mode
220 ; 2 = Port drivers are off in Powerdown mode
221 ; 3 = reserved
222 ;
223 ; <o> PFCFG: Program Flash Configuration (SYSCON1.4 .. SYSCON1.5)
224 ; <0=> Program Flash always ON <1=>Program Flash OFF in IDLE/Sleep mode
0000 225 _PFCFG EQU 0 ; 0 = Program Flash is always ON (default)
226 ; 1 = Program Flash is off in IDLE or Sleep mode
227 ; 2 - 3 = reserved
228 ;
229 ; <o> CPSYS: Clock Prescaler for System (SYSCON1.8 .. SYSCON1.10)
230 ; <0=>CPU clock = PLL frequency <1=>CPU clock = PLL frequency / 2
0000 231 _CPSYS EQU 0 ; 0 = clock signal for CPU is PLL frequency
232 ; 1 = clock signal for CPU is PLL frequency / 2
233 ; 2 - 7 = reserved
234 ; </e>
235 ;
236 ; <e> Definitions for System Configuration Register SYSCON3
237 ; =========================================================
238 ;
239 ; INIT_SYSCON3: Init SYSCON3 register
240 ; --- Set INIT_SYSCON3 = 1 to initilize the SYSCON3 register
241 $SET (INIT_SYSCON3 = 1)
242 ;
243 ; SYSCON3: Power Management (disable on-chip peripherals)
244 ;
245 ;<q> Disable Analog/Digital Converter
0000 246 ADCDIS EQU 0 ; 1 = disable Analog/Digital Converter (SYSCON3.0)
247 ;<q> Disable UART ASC0
0000 248 ASC0DIS EQU 0 ; 1 = disable UART ASC0 (SYSCON3.1)
249 ;<q> Disable Synchronus Serial Cnl0 SSC0
0000 250 SSC0DIS EQU 0 ; 1 = disable Synchronus Serial Cnl0 SSC0 (SYSCON3.2)
251 ;<q> Disable Timer Block GPT
0000 252 GPTDIS EQU 0 ; 1 = disable Timer Block GPT (SYSCON3.3)
253 ; reserved (SYSCON3.4)
254 ;<q> Disable on-chip Flash Memory Module
0000 255 FMDIS EQU 0 ; 1 = disable on-chip Flash Memory Module (SYSCON3.5)
256 ;<q> Disable CAPCOM Unit 1
A166 MACRO ASSEMBLER START_V2 09/02/2008 15:32:01 PAGE 5
0000 257 CC1DIS EQU 0 ; 1 = disable CAPCOM Unit 1 (SYSCON3.6)
258 ;<q> Disable CAPCOM Unit 2
0000 259 CC2DIS EQU 0 ; 1 = disable CAPCOM Unit 2 (SYSCON3.7)
260 ;<q> Disable CAPCOM Unit 6
0000 261 CC6DIS EQU 0 ; 1 = disable CAPCOM Unit 6 (SYSCON3.8)
262 ; reserved (SYSCON3.9)
263 ;<q> Disable UART ASC1
0000 264 ASC1DIS EQU 0 ; 1 = disable UART ASC1 (SYSCON3.10)
265 ;<q> Disable I2C Bus Module
0000 266 I2CDIS EQU 0 ; 1 = disable I2C Bus Module (SYSCON3.11)
267 ;<q> Disable SDLM (J1850) Module
0000 268 SDLMDIS EQU 0 ; 1 = disable SDLM (J1850) Module (SYSCON3.12)
269 ;<q> Disable on-chip CAN Module
0000 270 CANDIS EQU 0 ; 1 = disable on-chip CAN Module (SYSCON3.13)
271 ; reserved (SYSCON3.14)
272 ;<q> Disable Synchronus Serial Cnl1 SSC1
0000 273 SSC1DIS EQU 0 ; 1 = disable Synchronus Serial Cnl1 SSC1 (SYSCON3.15)
274 ;
275 ;</e>
276 ;</h>
277 ; <e> Definitions for Reset Configuration Register RSTCON
278 ; ===================================================
279 ;
280 ; INIT_RSTCON: Init RSTCON register
281 ; --- Set INIT_RSTCON = 0 to initilize the RSTCON register
282 $SET (INIT_RSTCON = 1)
283 ;
284 ; <o> RSTLEN: Reset Length Control (RSTCON.0 .. RSTCON.2)
285 ; <0=> 2 CPU clocks <1=> 4 CPU clocks <2=> 8 CPU clocks <3=> 16 CPU clocks
286 ; <4=> 32 CPU clocks <5=> 64 CPU clocks <6=> 128 CPU clocks <7=> 256 CPU clocks
0000 287 _RSTLEN EQU 0 ; 0 = 2 t_CPU clocks (default)
288 ; 1 = 4 t_CPU clocks
289 ; 2 = 8 t_CPU clocks
290 ; 3 = 16 t_CPU clocks
291 ; 4 = 32 t_CPU clocks
292 ; 5 = 64 t_CPU clocks
293 ; 6 = 128 t_CPU clocks
294 ; 7 = 256 t_CPU clocks
295 ;
296 ; <o> RORMV: RSTOUT# Remove Control (RSTCON.4)
297 ; <0=> RSTOUT delivers RSTOUT# signal <1=> RSTOUT pin operates as GPIO
0000 298 _RORMV EQU 0 ; 0 = RSTOUT delivers RSTOUT# signal
299 ; 1 = RSTOUT pin operates as GPIO
300 ;
301 ; <o> ROCOFF: RSTOUT# Control Switch Off (RSTCON.5)
302 ; <0=>RSTOUT deactivated by user software <1=>RSTOUT deactivated after reset
0001 303 _ROCOFF EQU 1 ; 0 = RSTOUT is deactivated by user software
304 ; 1 = RSTOUT is deactivated at end of reset
305 ;
306 ; <o> ROCON: RSTOUT# Control Switch Off (RSTCON.6)
307 ; <0=> RSTOUT active on any reset <1=> RSTOUT active on hardware reset
0001 308 _ROCON EQU 1 ; 0 = RSTOUT is activated upon any reset
309 ; 1 = RSTOUT is only activated upon a hardware reset
310 ;
311 ; <q> RODIS: RSTOUT# Disable Control (RSTCON.7) <0-1>
0000 312 _RODIS EQU 0 ; 0 = RSTOUT is controlled by other mechanism
313 ; 1 = RSTOUT is deactivated
314 ;
315 ;</e>
316 ;
317 ;
318 ; <e> Definitions for PLL Control Register PLLCON
319 ; ===============================================
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