arm_iss.cpp

這是一個arm模擬器 以C++實做 主要模擬ARM9架構

	tmp32 = (val32=READ_REG(rm), (val32>>shift_imm)|(val32<<(32-shift_imm)));
	val32  = READ_REG(rn);
	rslt32 = val32 + tmp32;
    if (rd==15)
        WRITE_CPSR(SPSR);
    else
		ASGN_NZCV(rslt32, rslt32<val32, (val32^tmp32^-1) & (val32^rslt32));
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(adds_lsl_mode3_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rs = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;

	uint32_t val32;
	uint32_t tmp32;
	uint32_t rslt32;


	tmp32 = (tmp32=READ_REG(rs)&0xFF, val32=READ_REG(rm), (tmp32<32)?(val32<<tmp32):0);
	val32  = READ_REG(rn);
	rslt32 = val32 + tmp32;
    if (rd==15)
        WRITE_CPSR(SPSR);
    else
		ASGN_NZCV(rslt32, rslt32<val32, (val32^tmp32^-1) & (val32^rslt32));
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(adds_lsr_mode3_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rs = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;

	uint32_t val32;
	uint32_t tmp32;
	uint32_t rslt32;


	tmp32 = (tmp32=READ_REG(rs)&0xFF, val32=READ_REG(rm), (tmp32<32)?(val32>>tmp32):0);
	val32  = READ_REG(rn);
	rslt32 = val32 + tmp32;
    if (rd==15)
        WRITE_CPSR(SPSR);
    else
		ASGN_NZCV(rslt32, rslt32<val32, (val32^tmp32^-1) & (val32^rslt32));
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(adds_asr_mode3_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rs = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;

	uint32_t val32;
	uint32_t tmp32;
	uint32_t rslt32;


	tmp32 = (tmp32=READ_REG(rs)&0xFF, val32=READ_REG(rm), (int32_t)val32>>(tmp32<32?tmp32:31));
	val32  = READ_REG(rn);
	rslt32 = val32 + tmp32;
    if (rd==15)
        WRITE_CPSR(SPSR);
    else
		ASGN_NZCV(rslt32, rslt32<val32, (val32^tmp32^-1) & (val32^rslt32));
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(adds_ror_mode3_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rs = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;

	uint32_t val32;
	uint32_t tmp32;
	uint32_t rslt32;


	tmp32 = (tmp32=READ_REG(rs)&0xFF, val32=READ_REG(rm), (val32>>(tmp32&0x1f))|(val32<<(32-(tmp32&0x1f))));
	val32  = READ_REG(rn);
	rslt32 = val32 + tmp32;
    if (rd==15)
        WRITE_CPSR(SPSR);
    else
		ASGN_NZCV(rslt32, rslt32<val32, (val32^tmp32^-1) & (val32^rslt32));
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(adci_imm_mode1_) (emulator_t *emu, target_inst_t inst)
{

	unsigned imm8 = (inst>>0)&255;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;



	WRITE_REG(rd, READ_REG(rn) + imm8 + C_FLAG);


}

void SIMIT_IMP(adci_rot_mode1_) (emulator_t *emu, target_inst_t inst)
{

	unsigned imm8 = (inst>>0)&255;
	unsigned rotate = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;



	WRITE_REG(rd, READ_REG(rn) + ((imm8>>(rotate<<1))|(imm8<<(32-(rotate<<1)))) + C_FLAG);


}

void SIMIT_IMP(adcis_imm_mode1_) (emulator_t *emu, target_inst_t inst)
{

	unsigned imm8 = (inst>>0)&255;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;

	uint32_t val32;
	uint32_t tmp32;
	uint32_t rslt32;
	uint32_t carry;


	tmp32  = imm8;
	val32  = READ_REG(rn);
	if (C_FLAG) {
		rslt32 = tmp32+val32+1;
		carry = rslt32 <= val32;
	}
	else {
		rslt32 = tmp32+val32;
		carry = rslt32 < val32;
	}
    if (rd==15)
        WRITE_CPSR(SPSR);
    else
		ASGN_NZCV(rslt32, carry, (val32 ^ tmp32 ^ -1) & (val32 ^ rslt32));
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(adcis_rot_mode1_) (emulator_t *emu, target_inst_t inst)
{

	unsigned imm8 = (inst>>0)&255;
	unsigned rotate = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;

	uint32_t val32;
	uint32_t tmp32;
	uint32_t rslt32;
	uint32_t carry;


	tmp32  = ((imm8>>(rotate<<1))|(imm8<<(32-(rotate<<1))));
	val32  = READ_REG(rn);
	if (C_FLAG) {
		rslt32 = tmp32+val32+1;
		carry = rslt32 <= val32;
	}
	else {
		rslt32 = tmp32+val32;
		carry = rslt32 < val32;
	}
    if (rd==15)
        WRITE_CPSR(SPSR);
    else
		ASGN_NZCV(rslt32, carry, (val32 ^ tmp32 ^ -1) & (val32 ^ rslt32));
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(adc_lsl_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned shift_imm = (inst>>7)&31;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;



	WRITE_REG(rd, READ_REG(rn) + (READ_REG(rm)<<shift_imm) + C_FLAG);


}

void SIMIT_IMP(adc_zero_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;



	WRITE_REG(rd, READ_REG(rn) + 0 + C_FLAG);


}

void SIMIT_IMP(adc_lsr_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned shift_imm = (inst>>7)&31;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;



	WRITE_REG(rd, READ_REG(rn) + (READ_REG(rm)>>shift_imm) + C_FLAG);


}

void SIMIT_IMP(adc_sign_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;



	WRITE_REG(rd, READ_REG(rn) + (BIT31(READ_REG(rm))?~0:0) + C_FLAG);


}

void SIMIT_IMP(adc_asr_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned shift_imm = (inst>>7)&31;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;



	WRITE_REG(rd, READ_REG(rn) + ((int32_t)(READ_REG(rm))>>shift_imm) + C_FLAG);


}

void SIMIT_IMP(adc_rrx_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;



	WRITE_REG(rd, READ_REG(rn) + ((READ_REG(rm)>>1)|(C_FLAG<<31)) + C_FLAG);


}

void SIMIT_IMP(adc_ror_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned shift_imm = (inst>>7)&31;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;

	uint32_t val32;


	WRITE_REG(rd, READ_REG(rn) + (val32=READ_REG(rm), (val32>>shift_imm)|(val32<<(32-shift_imm))) + C_FLAG);


}

void SIMIT_IMP(adc_lsl_mode3_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rs = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;

	uint32_t val32;
	uint32_t tmp32;


	WRITE_REG(rd, READ_REG(rn) + (tmp32=READ_REG(rs)&0xFF, val32=READ_REG(rm), (tmp32<32)?(val32<<tmp32):0) + C_FLAG);


}

void SIMIT_IMP(adc_lsr_mode3_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rs = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;

	uint32_t val32;
	uint32_t tmp32;


	WRITE_REG(rd, READ_REG(rn) + (tmp32=READ_REG(rs)&0xFF, val32=READ_REG(rm), (tmp32<32)?(val32>>tmp32):0) + C_FLAG);


}

void SIMIT_IMP(adc_asr_mode3_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rs = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;

	uint32_t val32;
	uint32_t tmp32;


	WRITE_REG(rd, READ_REG(rn) + (tmp32=READ_REG(rs)&0xFF, val32=READ_REG(rm), (int32_t)val32>>(tmp32<32?tmp32:31)) + C_FLAG);


}

void SIMIT_IMP(adc_ror_mode3_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rs = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;

	uint32_t val32;
	uint32_t tmp32;


	WRITE_REG(rd, READ_REG(rn) + (tmp32=READ_REG(rs)&0xFF, val32=READ_REG(rm), (val32>>(tmp32&0x1f))|(val32<<(32-(tmp32&0x1f)))) + C_FLAG);


}

void SIMIT_IMP(adcs_lsl_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned shift_imm = (inst>>7)&31;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;

	uint32_t val32;
	uint32_t tmp32;
	uint32_t rslt32;
	uint32_t carry;


	tmp32  = (READ_REG(rm)<<shift_imm);
	val32  = READ_REG(rn);
	if (C_FLAG) {
		rslt32 = tmp32+val32+1;
		carry = rslt32 <= val32;
	}
	else {
		rslt32 = tmp32+val32;
		carry = rslt32 < val32;
	}
    if (rd==15)
        WRITE_CPSR(SPSR);
    else
		ASGN_NZCV(rslt32, carry, (val32 ^ tmp32 ^ -1) & (val32 ^ rslt32));
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(adcs_zero_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;

	uint32_t val32;
	uint32_t tmp32;
	uint32_t rslt32;
	uint32_t carry;


	tmp32  = 0;
	val32  = READ_REG(rn);
	if (C_FLAG) {
		rslt32 = tmp32+val32+1;
		carry = rslt32 <= val32;
	}
	else {
		rslt32 = tmp32+val32;
		carry = rslt32 < val32;
	}
    if (rd==15)
        WRITE_CPSR(SPSR);
    else
		ASGN_NZCV(rslt32, carry, (val32 ^ tmp32 ^ -1) & (val32 ^ rslt32));
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(adcs_lsr_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned shift_imm = (inst>>7)&31;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;

	uint32_t val32;
	uint32_t tmp32;
	uint32_t rslt32;
	uint32_t carry;


	tmp32  = (READ_REG(rm)>>shift_imm);
	val32  = READ_REG(rn);
	if (C_FLAG) {
		rslt32 = tmp32+val32+1;
		carry = rslt32 <= val32;
	}
	else {
		rslt32 = tmp32+val32;
		carry = rslt32 < val32;
	}
    if (rd==15)
        WRITE_CPSR(SPSR);
    else
		ASGN_NZCV(rslt32, carry, (val32 ^ tmp32 ^ -1) & (val32 ^ rslt32));
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(adcs_sign_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;

	uint32_t val32;
	uint32_t tmp32;
	uint32_t rslt32;
	uint32_t carry;


	tmp32  = (BIT31(READ_REG(rm))?~0:0);
	val32  = READ_REG(rn);
	if (C_FLAG) {
		rslt32 = tmp32+val32+1;
		carry = rslt32 <= val32;
	}
	else {
		rslt32 = tmp32+val32;
		carry = rslt32 < val32;
	}
    if (rd==15)
        WRITE_CPSR(SPSR);
    else
		ASGN_NZCV(rslt32, carry, (val32 ^ tmp32 ^ -1) & (val32 ^ rslt32));
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(adcs_asr_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned shift_imm = (inst>>7)&31;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;

	uint32_t val32;
	uint32_t tmp32;
	uint32_t rslt32;
	uint32_t carry;


	tmp32  = ((int32_t)(READ_REG(rm))>>shift_imm);
	val32  = READ_REG(rn);
	if (C_FLAG) {
		rslt32 = tmp32+val32+1;
		carry = rslt32 <= val32;
	}
	else {
		rslt32 = tmp32+val32;
		carry = rslt32 < val32;
	}
    if (rd==15)
        WRITE_CPSR(SPSR);
    else
		ASGN_NZCV(rslt32, carry, (val32 ^ tmp32 ^ -1) & (val32 ^ rslt32));
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(adcs_rrx_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;

	uint32_t val32;
	uint32_t tmp32;
	uint32_t rslt32;
	uint32_t carry;


	tmp32  = ((READ_REG(rm)>>1)|(C_FLAG<<31));
	val32  = READ_REG(rn);
	if (C_FLAG) {
		rslt32 = tmp32+val32+1;
		carry = rslt32 <= val32;
	}
	else {
		rslt32 = tmp32+val32;
		carry = rslt32 < val32;
	}
    if (rd==15)
        WRITE_CPSR(SPSR);
    else
		ASGN_NZCV(rslt32, carry, (val32 ^ tmp32 ^ -1) & (val32 ^ rslt32));
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(adcs_ror_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned shift_imm = (inst>>7)&31;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;

	uint32_t val32;
	uint32_t tmp32;
	uint32_t rslt32;
	uint32_t carry;


	tmp32  = (val32=READ_REG(rm), (val32>>shift_imm)|(val32<<(32-shift_imm)));
	val32  = READ_REG(rn);
	if (C_FLAG) {
		rslt32 = tmp32+val32+1;
		carry = rslt32 <= val32;
	}
	else {
		rslt32 = tmp32+val32;
		carry = rslt32 < val32;
	}
    if (rd==15)
        WRITE_CPSR(SPSR);
    else
		ASGN_NZCV(rslt32, carry, (val32 ^ tmp32 ^ -1) & (val32 ^ rslt32));
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(adcs_lsl_mode3_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rs = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;

	uint32_t val32;
	uint32_t tmp32;
	uint32_t rslt32;
	uint32_t carry;


	tmp32  = (tmp32=READ_REG(rs)&0xFF, val32=READ_REG(rm), (tmp32<32)?(val32<<tmp32):0);
	val32  = READ_REG(rn);
	if (C_FLAG) {
		rslt32 = tmp32+val32+1;
		carry = rslt32 <= val32;
	}
	else {
		rslt32 = tmp32+val32;
		carry = rslt32 < val32;
	}
    if (rd==15)
        WRITE_CPSR(SPSR);
    else
		ASGN_NZCV(rslt32, carry, (val32 ^ tmp32 ^ -1) & (val32 ^ rslt32));
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(adcs_lsr_mode3_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rs = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;

	uint32_t val32;
	uint32_t tmp32;
	uint32_t rslt32;
	uint32_t carry;


	tmp32  = (tmp32=READ_REG(rs)&0xFF, val32=READ_REG(rm), (tmp32<32)?(val32>>tmp32):0);
	val32  = READ_REG(rn);
	if (C_FLAG) {
		rslt32 = tmp32+val32+1;
		carry = rslt32 <= val32;
	}
	else {
		rslt32 = tmp32+val32;
		carry = rslt32 < val32;
	}
    if (rd==15)
        WRITE_CPSR(SPSR);
    else
		ASGN_NZCV(rslt32, carry, (val32 ^ tmp32 ^ -1) & (val32 ^ rslt32));
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(adcs_asr_mode3_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rs = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;

	uint32_t val32;
	uint32_t tmp32;
	uint32_t rslt32;
	uint32_t carry;


	tmp32  = (tmp32=READ_REG(rs)&0xFF, val32=READ_REG(rm), (int32_t)val32>>(tmp32<32?tmp32:31));
	val32  = READ_REG(rn);
	if (C_FLAG) {
		rslt32 = tmp32+val32+1;
		carry = rslt32 <= val32;
	}
	else {
		rslt32 = tmp32+val32;
		carry = rslt32 < val32;
	}
    if (rd==15)
        WRITE_CPSR(SPSR);
    else
		ASGN_NZCV(rslt32, carry, (val32 ^ tmp32 ^ -1) & (val32 ^ rslt32));
	WRITE_REG(rd, rslt32);