arm_iss.cpp

這是一個arm模擬器 以C++實做 主要模擬ARM9架構

{

	unsigned rm = (inst>>0)&15;
	unsigned rs = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;

	uint32_t val32;
	uint32_t tmp32;


	WRITE_REG(rd, ~(tmp32=READ_REG(rs)&0xFF, val32=READ_REG(rm), (int32_t)val32>>(tmp32<32?tmp32:31)));


}

void SIMIT_IMP(mvn_ror_mode3_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rs = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;

	uint32_t val32;
	uint32_t tmp32;


	WRITE_REG(rd, ~(tmp32=READ_REG(rs)&0xFF, val32=READ_REG(rm), (val32>>(tmp32&0x1f))|(val32<<(32-(tmp32&0x1f)))));


}

void SIMIT_IMP(mvns_lsz_mode2_s_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rd = (inst>>12)&15;

	uint32_t rslt32;
	uint32_t carry;


	rslt32 = ~(carry=C_FLAG, READ_REG(rm));
    if (rd==15)
        WRITE_CPSR(SPSR);
    else
		ASGN_NZC(rslt32, carry);
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(mvns_lsl_mode2_s_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned shift_imm = (inst>>7)&31;
	unsigned rd = (inst>>12)&15;

	uint32_t val32;
	uint32_t rslt32;
	uint32_t carry;


	rslt32 = ~(val32=READ_REG(rm), carry=BITn(val32, 32-shift_imm), val32<<shift_imm);
    if (rd==15)
        WRITE_CPSR(SPSR);
    else
		ASGN_NZC(rslt32, carry);
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(mvns_zero_mode2_s_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rd = (inst>>12)&15;

	uint32_t rslt32;
	uint32_t carry;


	rslt32 = ~(carry=BIT31(READ_REG(rm)), 0);
    if (rd==15)
        WRITE_CPSR(SPSR);
    else
		ASGN_NZC(rslt32, carry);
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(mvns_lsr_mode2_s_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned shift_imm = (inst>>7)&31;
	unsigned rd = (inst>>12)&15;

	uint32_t val32;
	uint32_t rslt32;
	uint32_t carry;


	rslt32 = ~(val32=READ_REG(rm), carry=BITn(val32, shift_imm-1), val32>>shift_imm);
    if (rd==15)
        WRITE_CPSR(SPSR);
    else
		ASGN_NZC(rslt32, carry);
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(mvns_sign_mode2_s_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rd = (inst>>12)&15;

	uint32_t val32;
	uint32_t rslt32;
	uint32_t carry;


	rslt32 = ~(val32=READ_REG(rm), carry=BIT31(val32), BIT31(val32)?~0:0);
    if (rd==15)
        WRITE_CPSR(SPSR);
    else
		ASGN_NZC(rslt32, carry);
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(mvns_asr_mode2_s_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned shift_imm = (inst>>7)&31;
	unsigned rd = (inst>>12)&15;

	uint32_t val32;
	uint32_t rslt32;
	uint32_t carry;


	rslt32 = ~(val32=READ_REG(rm), carry=BITn(val32, shift_imm-1), (int32_t)val32>>shift_imm);
    if (rd==15)
        WRITE_CPSR(SPSR);
    else
		ASGN_NZC(rslt32, carry);
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(mvns_rrx_mode2_s_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rd = (inst>>12)&15;

	uint32_t val32;
	uint32_t rslt32;
	uint32_t carry;


	rslt32 = ~(val32=READ_REG(rm), carry=BIT0(val32), (val32>>1)|(C_FLAG<<31));
    if (rd==15)
        WRITE_CPSR(SPSR);
    else
		ASGN_NZC(rslt32, carry);
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(mvns_ror_mode2_s_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned shift_imm = (inst>>7)&31;
	unsigned rd = (inst>>12)&15;

	uint32_t val32;
	uint32_t rslt32;
	uint32_t carry;


	rslt32 = ~(val32=READ_REG(rm), carry=BITn(val32, shift_imm-1), (val32>>shift_imm)|(val32<<(32-shift_imm)));
    if (rd==15)
        WRITE_CPSR(SPSR);
    else
		ASGN_NZC(rslt32, carry);
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(mvns_lsl_mode3_s_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rs = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;

	uint32_t val32;
	uint32_t tmp32;
	uint32_t rslt32;
	uint32_t carry;


	rslt32 = ~(tmp32=READ_REG(rs)&0xFF, val32=READ_REG(rm), carry=(tmp32==0)?C_FLAG:((tmp32>32)?0:BITn(val32,32-val32)), (tmp32<32)?(val32<<tmp32):0);
    if (rd==15)
        WRITE_CPSR(SPSR);
    else
		ASGN_NZC(rslt32, carry);
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(mvns_lsr_mode3_s_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rs = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;

	uint32_t val32;
	uint32_t tmp32;
	uint32_t rslt32;
	uint32_t carry;


	rslt32 = ~(tmp32=READ_REG(rs)&0xFF, val32=READ_REG(rm), carry=(tmp32==0)?C_FLAG:((tmp32>32)?0:BITn(val32,tmp32-1)), (tmp32<32)?(val32>>tmp32):0);
    if (rd==15)
        WRITE_CPSR(SPSR);
    else
		ASGN_NZC(rslt32, carry);
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(mvns_asr_mode3_s_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rs = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;

	uint32_t val32;
	uint32_t tmp32;
	uint32_t rslt32;
	uint32_t carry;


	rslt32 = ~(tmp32=READ_REG(rs)&0xFF, val32=READ_REG(rm), carry=(tmp32==0)?C_FLAG:((tmp32>31)?BIT31(val32):BITn(val32,tmp32-1)), (int32_t)val32>>(tmp32<32?tmp32:31));
    if (rd==15)
        WRITE_CPSR(SPSR);
    else
		ASGN_NZC(rslt32, carry);
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(mvns_ror_mode3_s_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rs = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;

	uint32_t val32;
	uint32_t tmp32;
	uint32_t rslt32;
	uint32_t carry;


	rslt32 = ~(tmp32=READ_REG(rs)&0xFF, val32=READ_REG(rm), carry=(tmp32==0)?C_FLAG:((tmp32&0x1f==0)?BIT31(val32):BITn(val32,(tmp32&0x1f)-1)), (val32>>(tmp32&0x1f))|(val32<<(32-(tmp32&0x1f))));
    if (rd==15)
        WRITE_CPSR(SPSR);
    else
		ASGN_NZC(rslt32, carry);
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(addi_imm_mode1_) (emulator_t *emu, target_inst_t inst)
{

	unsigned imm8 = (inst>>0)&255;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;



	WRITE_REG(rd, READ_REG(rn) + imm8);


}

void SIMIT_IMP(addi_rot_mode1_) (emulator_t *emu, target_inst_t inst)
{

	unsigned imm8 = (inst>>0)&255;
	unsigned rotate = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;



	WRITE_REG(rd, READ_REG(rn) + ((imm8>>(rotate<<1))|(imm8<<(32-(rotate<<1)))));


}

void SIMIT_IMP(addis_imm_mode1_) (emulator_t *emu, target_inst_t inst)
{

	unsigned imm8 = (inst>>0)&255;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;

	uint32_t val32;
	uint32_t tmp32;
	uint32_t rslt32;


	tmp32 = imm8;
	val32  = READ_REG(rn);
	rslt32 = val32 + tmp32;
    if (rd==15)
        WRITE_CPSR(SPSR);
    else
		ASGN_NZCV(rslt32, rslt32<val32, (val32^tmp32^-1) & (val32^rslt32));
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(addis_rot_mode1_) (emulator_t *emu, target_inst_t inst)
{

	unsigned imm8 = (inst>>0)&255;
	unsigned rotate = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;

	uint32_t val32;
	uint32_t tmp32;
	uint32_t rslt32;


	tmp32 = ((imm8>>(rotate<<1))|(imm8<<(32-(rotate<<1))));
	val32  = READ_REG(rn);
	rslt32 = val32 + tmp32;
    if (rd==15)
        WRITE_CPSR(SPSR);
    else
		ASGN_NZCV(rslt32, rslt32<val32, (val32^tmp32^-1) & (val32^rslt32));
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(add_lsl_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned shift_imm = (inst>>7)&31;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;



	WRITE_REG(rd, READ_REG(rn) + (READ_REG(rm)<<shift_imm));


}

void SIMIT_IMP(add_zero_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;



	WRITE_REG(rd, READ_REG(rn) + 0);


}

void SIMIT_IMP(add_lsr_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned shift_imm = (inst>>7)&31;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;



	WRITE_REG(rd, READ_REG(rn) + (READ_REG(rm)>>shift_imm));


}

void SIMIT_IMP(add_sign_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;



	WRITE_REG(rd, READ_REG(rn) + (BIT31(READ_REG(rm))?~0:0));


}

void SIMIT_IMP(add_asr_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned shift_imm = (inst>>7)&31;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;



	WRITE_REG(rd, READ_REG(rn) + ((int32_t)(READ_REG(rm))>>shift_imm));


}

void SIMIT_IMP(add_rrx_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;



	WRITE_REG(rd, READ_REG(rn) + ((READ_REG(rm)>>1)|(C_FLAG<<31)));


}

void SIMIT_IMP(add_ror_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned shift_imm = (inst>>7)&31;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;

	uint32_t val32;


	WRITE_REG(rd, READ_REG(rn) + (val32=READ_REG(rm), (val32>>shift_imm)|(val32<<(32-shift_imm))));


}

void SIMIT_IMP(add_lsl_mode3_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rs = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;

	uint32_t val32;
	uint32_t tmp32;


	WRITE_REG(rd, READ_REG(rn) + (tmp32=READ_REG(rs)&0xFF, val32=READ_REG(rm), (tmp32<32)?(val32<<tmp32):0));


}

void SIMIT_IMP(add_lsr_mode3_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rs = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;

	uint32_t val32;
	uint32_t tmp32;


	WRITE_REG(rd, READ_REG(rn) + (tmp32=READ_REG(rs)&0xFF, val32=READ_REG(rm), (tmp32<32)?(val32>>tmp32):0));


}

void SIMIT_IMP(add_asr_mode3_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rs = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;

	uint32_t val32;
	uint32_t tmp32;


	WRITE_REG(rd, READ_REG(rn) + (tmp32=READ_REG(rs)&0xFF, val32=READ_REG(rm), (int32_t)val32>>(tmp32<32?tmp32:31)));


}

void SIMIT_IMP(add_ror_mode3_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rs = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;

	uint32_t val32;
	uint32_t tmp32;


	WRITE_REG(rd, READ_REG(rn) + (tmp32=READ_REG(rs)&0xFF, val32=READ_REG(rm), (val32>>(tmp32&0x1f))|(val32<<(32-(tmp32&0x1f)))));


}

void SIMIT_IMP(adds_lsl_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned shift_imm = (inst>>7)&31;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;

	uint32_t val32;
	uint32_t tmp32;
	uint32_t rslt32;


	tmp32 = (READ_REG(rm)<<shift_imm);
	val32  = READ_REG(rn);
	rslt32 = val32 + tmp32;
    if (rd==15)
        WRITE_CPSR(SPSR);
    else
		ASGN_NZCV(rslt32, rslt32<val32, (val32^tmp32^-1) & (val32^rslt32));
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(adds_zero_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;

	uint32_t val32;
	uint32_t tmp32;
	uint32_t rslt32;


	tmp32 = 0;
	val32  = READ_REG(rn);
	rslt32 = val32 + tmp32;
    if (rd==15)
        WRITE_CPSR(SPSR);
    else
		ASGN_NZCV(rslt32, rslt32<val32, (val32^tmp32^-1) & (val32^rslt32));
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(adds_lsr_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned shift_imm = (inst>>7)&31;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;

	uint32_t val32;
	uint32_t tmp32;
	uint32_t rslt32;


	tmp32 = (READ_REG(rm)>>shift_imm);
	val32  = READ_REG(rn);
	rslt32 = val32 + tmp32;
    if (rd==15)
        WRITE_CPSR(SPSR);
    else
		ASGN_NZCV(rslt32, rslt32<val32, (val32^tmp32^-1) & (val32^rslt32));
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(adds_sign_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;

	uint32_t val32;
	uint32_t tmp32;
	uint32_t rslt32;


	tmp32 = (BIT31(READ_REG(rm))?~0:0);
	val32  = READ_REG(rn);
	rslt32 = val32 + tmp32;
    if (rd==15)
        WRITE_CPSR(SPSR);
    else
		ASGN_NZCV(rslt32, rslt32<val32, (val32^tmp32^-1) & (val32^rslt32));
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(adds_asr_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned shift_imm = (inst>>7)&31;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;

	uint32_t val32;
	uint32_t tmp32;
	uint32_t rslt32;


	tmp32 = ((int32_t)(READ_REG(rm))>>shift_imm);
	val32  = READ_REG(rn);
	rslt32 = val32 + tmp32;
    if (rd==15)
        WRITE_CPSR(SPSR);
    else
		ASGN_NZCV(rslt32, rslt32<val32, (val32^tmp32^-1) & (val32^rslt32));
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(adds_rrx_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;

	uint32_t val32;
	uint32_t tmp32;
	uint32_t rslt32;


	tmp32 = ((READ_REG(rm)>>1)|(C_FLAG<<31));
	val32  = READ_REG(rn);
	rslt32 = val32 + tmp32;
    if (rd==15)
        WRITE_CPSR(SPSR);
    else
		ASGN_NZCV(rslt32, rslt32<val32, (val32^tmp32^-1) & (val32^rslt32));
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(adds_ror_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned shift_imm = (inst>>7)&31;
	unsigned rd = (inst>>12)&15;
	unsigned rn = (inst>>16)&15;

	uint32_t val32;
	uint32_t tmp32;
	uint32_t rslt32;