arm_iss.cpp

這是一個arm模擬器 以C++實做 主要模擬ARM9架構

/*************************************************************************
    Copyright (C) 2002 - 2007 Wei Qin
    See file COPYING for more information.

    This program is free software; you can redistribute it and/or modify    
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
*************************************************************************/
#include "arch.hpp"
void SIMIT_IMP(movi_imm_mode1_) (emulator_t *emu, target_inst_t inst)
{

	unsigned imm8 = (inst>>0)&255;
	unsigned rd = (inst>>12)&15;



	WRITE_REG(rd, imm8);


}

void SIMIT_IMP(movi_rot_mode1_) (emulator_t *emu, target_inst_t inst)
{

	unsigned imm8 = (inst>>0)&255;
	unsigned rotate = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;



	WRITE_REG(rd, ((imm8>>(rotate<<1))|(imm8<<(32-(rotate<<1)))));


}

void SIMIT_IMP(movis_imm_mode1_s_) (emulator_t *emu, target_inst_t inst)
{

	unsigned imm8 = (inst>>0)&255;
	unsigned rd = (inst>>12)&15;

	uint32_t rslt32;
	uint32_t carry;


	rslt32 = (carry=C_FLAG,imm8);
	if (rd==15)
		WRITE_CPSR(SPSR);
	else
		ASGN_NZC(rslt32, carry);
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(movis_rot_mode1_s_) (emulator_t *emu, target_inst_t inst)
{

	unsigned imm8 = (inst>>0)&255;
	unsigned rotate = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;

	uint32_t rslt32;
	uint32_t carry;


	rslt32 = (rslt32=(imm8>>(rotate<<1))|(imm8<<(32-(rotate<<1))), carry=BIT31(rslt32), rslt32);
	if (rd==15)
		WRITE_CPSR(SPSR);
	else
		ASGN_NZC(rslt32, carry);
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(mov_lsl_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned shift_imm = (inst>>7)&31;
	unsigned rd = (inst>>12)&15;



	WRITE_REG(rd, (READ_REG(rm)<<shift_imm));


}

void SIMIT_IMP(mov_zero_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rd = (inst>>12)&15;



	WRITE_REG(rd, 0);


}

void SIMIT_IMP(mov_lsr_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned shift_imm = (inst>>7)&31;
	unsigned rd = (inst>>12)&15;



	WRITE_REG(rd, (READ_REG(rm)>>shift_imm));


}

void SIMIT_IMP(mov_sign_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rd = (inst>>12)&15;



	WRITE_REG(rd, (BIT31(READ_REG(rm))?~0:0));


}

void SIMIT_IMP(mov_asr_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned shift_imm = (inst>>7)&31;
	unsigned rd = (inst>>12)&15;



	WRITE_REG(rd, ((int32_t)(READ_REG(rm))>>shift_imm));


}

void SIMIT_IMP(mov_rrx_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rd = (inst>>12)&15;



	WRITE_REG(rd, ((READ_REG(rm)>>1)|(C_FLAG<<31)));


}

void SIMIT_IMP(mov_ror_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned shift_imm = (inst>>7)&31;
	unsigned rd = (inst>>12)&15;

	uint32_t val32;


	WRITE_REG(rd, (val32=READ_REG(rm), (val32>>shift_imm)|(val32<<(32-shift_imm))));


}

void SIMIT_IMP(mov_lsl_mode3_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rs = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;

	uint32_t val32;
	uint32_t tmp32;


	WRITE_REG(rd, (tmp32=READ_REG(rs)&0xFF, val32=READ_REG(rm), (tmp32<32)?(val32<<tmp32):0));


}

void SIMIT_IMP(mov_lsr_mode3_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rs = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;

	uint32_t val32;
	uint32_t tmp32;


	WRITE_REG(rd, (tmp32=READ_REG(rs)&0xFF, val32=READ_REG(rm), (tmp32<32)?(val32>>tmp32):0));


}

void SIMIT_IMP(mov_asr_mode3_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rs = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;

	uint32_t val32;
	uint32_t tmp32;


	WRITE_REG(rd, (tmp32=READ_REG(rs)&0xFF, val32=READ_REG(rm), (int32_t)val32>>(tmp32<32?tmp32:31)));


}

void SIMIT_IMP(mov_ror_mode3_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rs = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;

	uint32_t val32;
	uint32_t tmp32;


	WRITE_REG(rd, (tmp32=READ_REG(rs)&0xFF, val32=READ_REG(rm), (val32>>(tmp32&0x1f))|(val32<<(32-(tmp32&0x1f)))));


}

void SIMIT_IMP(movs_lsz_mode2_s_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rd = (inst>>12)&15;

	uint32_t rslt32;
	uint32_t carry;


	rslt32 = (carry=C_FLAG, READ_REG(rm));
	if (rd==15)
    	WRITE_CPSR(SPSR);
	else
		ASGN_NZC(rslt32, carry);
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(movs_lsl_mode2_s_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned shift_imm = (inst>>7)&31;
	unsigned rd = (inst>>12)&15;

	uint32_t val32;
	uint32_t rslt32;
	uint32_t carry;


	rslt32 = (val32=READ_REG(rm), carry=BITn(val32, 32-shift_imm), val32<<shift_imm);
	if (rd==15)
    	WRITE_CPSR(SPSR);
	else
		ASGN_NZC(rslt32, carry);
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(movs_zero_mode2_s_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rd = (inst>>12)&15;

	uint32_t rslt32;
	uint32_t carry;


	rslt32 = (carry=BIT31(READ_REG(rm)), 0);
	if (rd==15)
    	WRITE_CPSR(SPSR);
	else
		ASGN_NZC(rslt32, carry);
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(movs_lsr_mode2_s_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned shift_imm = (inst>>7)&31;
	unsigned rd = (inst>>12)&15;

	uint32_t val32;
	uint32_t rslt32;
	uint32_t carry;


	rslt32 = (val32=READ_REG(rm), carry=BITn(val32, shift_imm-1), val32>>shift_imm);
	if (rd==15)
    	WRITE_CPSR(SPSR);
	else
		ASGN_NZC(rslt32, carry);
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(movs_sign_mode2_s_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rd = (inst>>12)&15;

	uint32_t val32;
	uint32_t rslt32;
	uint32_t carry;


	rslt32 = (val32=READ_REG(rm), carry=BIT31(val32), BIT31(val32)?~0:0);
	if (rd==15)
    	WRITE_CPSR(SPSR);
	else
		ASGN_NZC(rslt32, carry);
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(movs_asr_mode2_s_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned shift_imm = (inst>>7)&31;
	unsigned rd = (inst>>12)&15;

	uint32_t val32;
	uint32_t rslt32;
	uint32_t carry;


	rslt32 = (val32=READ_REG(rm), carry=BITn(val32, shift_imm-1), (int32_t)val32>>shift_imm);
	if (rd==15)
    	WRITE_CPSR(SPSR);
	else
		ASGN_NZC(rslt32, carry);
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(movs_rrx_mode2_s_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rd = (inst>>12)&15;

	uint32_t val32;
	uint32_t rslt32;
	uint32_t carry;


	rslt32 = (val32=READ_REG(rm), carry=BIT0(val32), (val32>>1)|(C_FLAG<<31));
	if (rd==15)
    	WRITE_CPSR(SPSR);
	else
		ASGN_NZC(rslt32, carry);
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(movs_ror_mode2_s_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned shift_imm = (inst>>7)&31;
	unsigned rd = (inst>>12)&15;

	uint32_t val32;
	uint32_t rslt32;
	uint32_t carry;


	rslt32 = (val32=READ_REG(rm), carry=BITn(val32, shift_imm-1), (val32>>shift_imm)|(val32<<(32-shift_imm)));
	if (rd==15)
    	WRITE_CPSR(SPSR);
	else
		ASGN_NZC(rslt32, carry);
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(movs_lsl_mode3_s_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rs = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;

	uint32_t val32;
	uint32_t tmp32;
	uint32_t rslt32;
	uint32_t carry;


	rslt32 = (tmp32=READ_REG(rs)&0xFF, val32=READ_REG(rm), carry=(tmp32==0)?C_FLAG:((tmp32>32)?0:BITn(val32,32-val32)), (tmp32<32)?(val32<<tmp32):0);
	if (rd==15)
    	WRITE_CPSR(SPSR);
	else
		ASGN_NZC(rslt32, carry);
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(movs_lsr_mode3_s_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rs = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;

	uint32_t val32;
	uint32_t tmp32;
	uint32_t rslt32;
	uint32_t carry;


	rslt32 = (tmp32=READ_REG(rs)&0xFF, val32=READ_REG(rm), carry=(tmp32==0)?C_FLAG:((tmp32>32)?0:BITn(val32,tmp32-1)), (tmp32<32)?(val32>>tmp32):0);
	if (rd==15)
    	WRITE_CPSR(SPSR);
	else
		ASGN_NZC(rslt32, carry);
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(movs_asr_mode3_s_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rs = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;

	uint32_t val32;
	uint32_t tmp32;
	uint32_t rslt32;
	uint32_t carry;


	rslt32 = (tmp32=READ_REG(rs)&0xFF, val32=READ_REG(rm), carry=(tmp32==0)?C_FLAG:((tmp32>31)?BIT31(val32):BITn(val32,tmp32-1)), (int32_t)val32>>(tmp32<32?tmp32:31));
	if (rd==15)
    	WRITE_CPSR(SPSR);
	else
		ASGN_NZC(rslt32, carry);
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(movs_ror_mode3_s_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rs = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;

	uint32_t val32;
	uint32_t tmp32;
	uint32_t rslt32;
	uint32_t carry;


	rslt32 = (tmp32=READ_REG(rs)&0xFF, val32=READ_REG(rm), carry=(tmp32==0)?C_FLAG:((tmp32&0x1f==0)?BIT31(val32):BITn(val32,(tmp32&0x1f)-1)), (val32>>(tmp32&0x1f))|(val32<<(32-(tmp32&0x1f))));
	if (rd==15)
    	WRITE_CPSR(SPSR);
	else
		ASGN_NZC(rslt32, carry);
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(mvni_imm_mode1_) (emulator_t *emu, target_inst_t inst)
{

	unsigned imm8 = (inst>>0)&255;
	unsigned rd = (inst>>12)&15;



	WRITE_REG(rd, ~imm8);


}

void SIMIT_IMP(mvni_rot_mode1_) (emulator_t *emu, target_inst_t inst)
{

	unsigned imm8 = (inst>>0)&255;
	unsigned rotate = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;



	WRITE_REG(rd, ~((imm8>>(rotate<<1))|(imm8<<(32-(rotate<<1)))));


}

void SIMIT_IMP(mvnis_imm_mode1_s_) (emulator_t *emu, target_inst_t inst)
{

	unsigned imm8 = (inst>>0)&255;
	unsigned rd = (inst>>12)&15;

	uint32_t rslt32;
	uint32_t carry;


	rslt32 = ~(carry=C_FLAG,imm8);
	if (rd==15)
		WRITE_CPSR(SPSR);
	else
		ASGN_NZC(rslt32, carry);
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(mvnis_rot_mode1_s_) (emulator_t *emu, target_inst_t inst)
{

	unsigned imm8 = (inst>>0)&255;
	unsigned rotate = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;

	uint32_t rslt32;
	uint32_t carry;


	rslt32 = ~(rslt32=(imm8>>(rotate<<1))|(imm8<<(32-(rotate<<1))), carry=BIT31(rslt32), rslt32);
	if (rd==15)
		WRITE_CPSR(SPSR);
	else
		ASGN_NZC(rslt32, carry);
	WRITE_REG(rd, rslt32);


}

void SIMIT_IMP(mvn_lsl_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned shift_imm = (inst>>7)&31;
	unsigned rd = (inst>>12)&15;



	WRITE_REG(rd, ~(READ_REG(rm)<<shift_imm));


}

void SIMIT_IMP(mvn_zero_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rd = (inst>>12)&15;



	WRITE_REG(rd, ~0);


}

void SIMIT_IMP(mvn_lsr_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned shift_imm = (inst>>7)&31;
	unsigned rd = (inst>>12)&15;



	WRITE_REG(rd, ~(READ_REG(rm)>>shift_imm));


}

void SIMIT_IMP(mvn_sign_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rd = (inst>>12)&15;



	WRITE_REG(rd, ~(BIT31(READ_REG(rm))?~0:0));


}

void SIMIT_IMP(mvn_asr_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned shift_imm = (inst>>7)&31;
	unsigned rd = (inst>>12)&15;



	WRITE_REG(rd, ~((int32_t)(READ_REG(rm))>>shift_imm));


}

void SIMIT_IMP(mvn_rrx_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rd = (inst>>12)&15;



	WRITE_REG(rd, ~((READ_REG(rm)>>1)|(C_FLAG<<31)));


}

void SIMIT_IMP(mvn_ror_mode2_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned shift_imm = (inst>>7)&31;
	unsigned rd = (inst>>12)&15;

	uint32_t val32;


	WRITE_REG(rd, ~(val32=READ_REG(rm), (val32>>shift_imm)|(val32<<(32-shift_imm))));


}

void SIMIT_IMP(mvn_lsl_mode3_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rs = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;

	uint32_t val32;
	uint32_t tmp32;


	WRITE_REG(rd, ~(tmp32=READ_REG(rs)&0xFF, val32=READ_REG(rm), (tmp32<32)?(val32<<tmp32):0));


}

void SIMIT_IMP(mvn_lsr_mode3_) (emulator_t *emu, target_inst_t inst)
{

	unsigned rm = (inst>>0)&15;
	unsigned rs = (inst>>8)&15;
	unsigned rd = (inst>>12)&15;

	uint32_t val32;
	uint32_t tmp32;


	WRITE_REG(rd, ~(tmp32=READ_REG(rs)&0xFF, val32=READ_REG(rm), (tmp32<32)?(val32>>tmp32):0));


}

void SIMIT_IMP(mvn_asr_mode3_) (emulator_t *emu, target_inst_t inst)