decode.cpp

這是一個arm模擬器 以C++實做 主要模擬ARM9架構

static char *disasm_ldst2_reg(arm_inst_t inst, arm_addr_t addr, char *buf)
{
	buf += sprintf(buf, "%s%s%s%s %s, ",
		LFLD?"ldr":"str", arm_conditional[COND], SIGN?"s":"", HFLD?"h":"b",
		arm_regnames[RDFLD]);

	/*immediate offset*/
	if (PFLD) {
		buf += sprintf(buf, "[%s, %s%s]",
			arm_regnames[RNFLD], UFLD?"":"-", arm_regnames[RMFLD]);
		if (WFLD)
			buf += sprintf(buf, "!");
	}
	else {
		buf += sprintf(buf, "[%s], %s%s",
			arm_regnames[RNFLD], UFLD?"":"-", arm_regnames[RMFLD]);
	}
	buf += sprintf(buf, ";\n");
	return buf;
}
	
static char *disasm_swap(arm_inst_t inst, arm_addr_t addr, char *buf)
{
    buf += sprintf(buf, "swp%s %s, %s, [%s];\n",
		arm_conditional[COND],
		arm_regnames[RDFLD], arm_regnames[RMFLD], arm_regnames[RNFLD]);
    return buf;
}

static char *disasm_swap_byte(arm_inst_t inst, arm_addr_t addr, char *buf)
{
    buf += sprintf(buf, "swp%sb %s, %s, [%s];\n",
		arm_conditional[COND],
		arm_regnames[RDFLD], arm_regnames[RMFLD], arm_regnames[RNFLD]);
    return buf;
}

static char *disasm_ldstm(arm_inst_t inst, arm_addr_t addr, char *buf)
{
	uint32_t i, first = 1;
	buf += sprintf(buf, "%s%s%s%s %s%s, {",
		LFLD?"ldm":"stm", arm_conditional[COND], UFLD?"i":"d", PFLD?"b":"a",
		arm_regnames[RNFLD], WFLD?"!":"");

	for (i = 0; i<16; i++) {
		if ((1<<i) & inst) {
			buf += sprintf(buf, "%s%s", first?"":", ", arm_regnames[i]);
			first = 0;
		}
	}
	buf += sprintf(buf, "}");

	if (BITn(inst,22))
		buf += sprintf(buf, "^");

	buf += sprintf(buf, ";\n");
	return buf;
}

/* multiplications */

static char *disasm_mla(arm_inst_t inst, arm_addr_t addr, char *buf)
{
	buf += sprintf(buf, "mla%s%s %s, %s, %s, %s;\n",
		arm_conditional[COND], SFLD?"s":"",
		arm_regnames[RNFLD], arm_regnames[RMFLD],
		arm_regnames[RSFLD], arm_regnames[RDFLD]); 
	return buf;
}

static char *disasm_mul(arm_inst_t inst, arm_addr_t addr, char *buf)
{
	buf += sprintf(buf, "mul%s%s %s, %s, %s;\n",
		arm_conditional[COND], SFLD?"s":"",
		arm_regnames[RNFLD], arm_regnames[RMFLD], arm_regnames[RSFLD]); 
	return buf;
}

static char *disasm_smull(arm_inst_t inst, arm_addr_t addr, char *buf)
{
	buf += sprintf(buf, "smull%s%s %s, %s, %s, %s;\n",
		arm_conditional[COND], SFLD?"s":"",
		arm_regnames[RDFLD], arm_regnames[RNFLD],
		arm_regnames[RMFLD], arm_regnames[RSFLD]); 
	return buf;
}

static char *disasm_smlal(arm_inst_t inst, arm_addr_t addr, char *buf)
{
	buf += sprintf(buf, "smlal%s%s %s, %s, %s, %s;\n",
		arm_conditional[COND], SFLD?"s":"",
		arm_regnames[RDFLD], arm_regnames[RNFLD],
		arm_regnames[RMFLD], arm_regnames[RSFLD]); 
	return buf;
}

static char *disasm_umull(arm_inst_t inst, arm_addr_t addr, char *buf)
{
	buf += sprintf(buf, "umull%s%s %s, %s, %s, %s;\n",
		arm_conditional[COND], SFLD?"s":"",
		arm_regnames[RDFLD], arm_regnames[RNFLD],
		arm_regnames[RMFLD], arm_regnames[RSFLD]); 
	return buf;
}

static char *disasm_umlal(arm_inst_t inst, arm_addr_t addr, char *buf)
{
	buf += sprintf(buf, "umlal%s%s %s, %s, %s, %s;\n",
		arm_conditional[COND], SFLD?"s":"",
		arm_regnames[RDFLD], arm_regnames[RNFLD],
		arm_regnames[RMFLD], arm_regnames[RSFLD]); 
	return buf;
}

/* branches */

static char *disasm_branch(arm_inst_t inst, arm_addr_t pc, char *buf)
{
	int32_t offset = (int32_t)(inst<<8)>>6;
	buf += sprintf(buf, "b%s 0x%x;\n",
		arm_conditional[COND], pc+8+offset);
	return buf;
}

static char *disasm_branch_link(arm_inst_t inst, arm_addr_t pc, char *buf)
{
	int32_t offset = (int32_t)(inst<<8)>>6;
	buf += sprintf(buf, "bl%s 0x%x;\n",
		arm_conditional[COND], pc+8+offset);
	return buf;
}


/* status registers */

static char *disasm_mrs(arm_inst_t inst, arm_addr_t addr, char *buf)
{
	buf += sprintf(buf, "mrs%s %s, CPSR;\n",
		arm_conditional[COND], arm_regnames[RDFLD]);
	return buf;
}

static char *disasm_mrs_r(arm_inst_t inst, arm_addr_t addr, char *buf)
{
	buf += sprintf(buf, "mrs%s %s, SPSR;\n",
		arm_conditional[COND], arm_regnames[RDFLD]);
	return buf;
}

/*0x32*/
static char *disasm_msr_1(arm_inst_t inst, arm_addr_t addr, char *buf)
{
    uint32_t operand;
    uint32_t imm = inst & 0xff;
    uint32_t shift = (inst>>7) & 0x1e;
	operand = (imm >> shift) | (imm << (32 - shift));
	buf += sprintf(buf, "msr%s CPSR_%s, #%u;\n",
		arm_conditional[COND], msr_fields[RNFLD], operand);
	return buf;
}

/*0x36*/
static char *disasm_msr_1r(arm_inst_t inst, arm_addr_t addr, char *buf)
{
    uint32_t operand;
    uint32_t imm = inst & 0xff;
    uint32_t shift = (inst>>7) & 0x1e;
	operand = (imm >> shift) | (imm << (32 - shift));
	buf += sprintf(buf, "msr%s SPSR_%s, #%u;\n",
		arm_conditional[COND], msr_fields[RNFLD], operand);
	return buf;
}

/*0x12*/
static char *disasm_msr_2(arm_inst_t inst, arm_addr_t addr, char *buf)
{
	buf += sprintf(buf, "msr%s CPSR_%s, %s;\n",
		arm_conditional[COND], msr_fields[RNFLD], arm_regnames[RMFLD]);
	return buf;
}

/*0x16*/
static char *disasm_msr_2r(arm_inst_t inst, arm_addr_t addr, char *buf)
{
	buf += sprintf(buf, "msr%s SPSR_%s, %s;\n",
		arm_conditional[COND], msr_fields[RNFLD], arm_regnames[RMFLD]);
	return buf;
}


/* coprocessor instruction */

static char *disasm_cdp(arm_inst_t inst, arm_addr_t addr, char *buf)
{
	buf += sprintf(buf, "cdp p%u, %u, cr%u, cr%u, cr%u, %u\n",
			RSFLD, (inst>>20)&15, RDFLD, RNFLD, RMFLD, (inst>>5)&7);
	return buf;
}

static char *disasm_mcr(arm_inst_t inst, arm_addr_t addr, char *buf)
{
	buf += sprintf(buf, "mcr p%u, %u, %s, cr%u, cr%u, %u\n",
			RSFLD, (inst>>21)&7, arm_regnames[RDFLD],
			RNFLD, RMFLD, (inst>>5)&7);
	return buf;
}

static char *disasm_mrc(arm_inst_t inst, arm_addr_t addr, char *buf)
{
	buf += sprintf(buf, "mrc p%u, %u, %s, cr%u, cr%u, %u\n",
			RSFLD, (inst>>21)&7, arm_regnames[RDFLD],
			RNFLD, RMFLD, (inst>>5)&7);
	return buf;
}

static char *disasm_ldc(arm_inst_t inst, arm_addr_t addr, char *buf)
{
	buf += sprintf(buf, "ldc p%u, cr%u, ", RSFLD, RDFLD);

	if (PFLD) {
		buf += sprintf(buf, "[%s, #%s%u]",
			arm_regnames[RNFLD], UFLD?"":"-", (inst&0xFF)<<2);
		if (WFLD)
			buf += sprintf(buf, "!");
	}
	else {
		if (WFLD)
			buf += sprintf(buf, "[%s], #%s%u",
				arm_regnames[RNFLD], UFLD?"":"-", (inst&0xFF)<<2);
		else
			buf += sprintf(buf, "[%s], {%u}",
				arm_regnames[RNFLD], inst&0xFF);
	}
	buf += sprintf(buf, ";\n");
	return buf;
}

static char *disasm_stc(arm_inst_t inst, arm_addr_t addr, char *buf)
{
	buf += sprintf(buf, "stc p%u, cr%u, ", RSFLD, RDFLD);

	if (PFLD) {
		buf += sprintf(buf, "[%s, #%s%u]",
			arm_regnames[RNFLD], UFLD?"":"-", (inst&0xFF)<<2);
		if (WFLD)
			buf += sprintf(buf, "!");
	}
	else {
		if (WFLD)
			buf += sprintf(buf, "[%s], #%s%u",
				arm_regnames[RNFLD], UFLD?"":"-", (inst&0xFF)<<2);
		else
			buf += sprintf(buf, "[%s], {%u}",
				arm_regnames[RNFLD], inst&0xFF);
	}
	buf += sprintf(buf, ";\n");
	return buf;
}

/* syscall */
static char *disasm_sc(arm_inst_t inst, target_addr_t pc, char *buf)
{
	buf += sprintf(buf, "swi %x;\n", (inst<<8)>>8);
	return buf;
}

static char *disasm_clz(arm_inst_t inst, arm_addr_t addr, char *buf)
{
	buf += sprintf(buf, "clz%s %s, %s\n",
		arm_conditional[COND], arm_regnames[RDFLD] ,arm_regnames[RMFLD]);
	return buf;
}

/* XScale instruction (MAR MRA) */
static char *disasm_mar(arm_inst_t inst, arm_addr_t addr, char *buf)
{
	buf += sprintf(buf, "mar%s acc0, %s, %s\n",
		arm_conditional[COND], arm_regnames[RDFLD] ,arm_regnames[RNFLD]);
	return buf;
}

static char *disasm_mra(arm_inst_t inst, arm_addr_t addr, char *buf)
{
	buf += sprintf(buf, "mra%s %s, %s, acc0\n",
		arm_conditional[COND], arm_regnames[RDFLD] ,arm_regnames[RNFLD]);
	return buf;
}

/* DSP instruction */
static char *disasm_ldstd_imm(arm_inst_t inst, arm_addr_t addr, char *buf)
{
	uint32_t offset = ((inst>>4) & 0xF0) | (inst & 0xF);

	buf += sprintf(buf, "%s%s%s %s, ",
		HFLD?"str":"ldr", arm_conditional[COND], "d",
		arm_regnames[RDFLD]);

	/*immediate offset*/
	if (PFLD) {
		buf += sprintf(buf, "[%s, #%s%u]",
			arm_regnames[RNFLD], UFLD?"":"-", offset);
		if (WFLD)
			buf += sprintf(buf, "!");
	}
	else {
		buf += sprintf(buf, "[%s], #%s%u",
			arm_regnames[RNFLD], UFLD?"":"-", offset);
	}
	buf += sprintf(buf, ";\n");
	return buf;
}

static char *disasm_ldstd_reg(arm_inst_t inst, arm_addr_t addr, char *buf)
{
	buf += sprintf(buf, "%s%s%s %s, ",
		HFLD?"str":"ldr", arm_conditional[COND], "d",
		arm_regnames[RDFLD]);

	/*immediate offset*/
	if (PFLD) {
		buf += sprintf(buf, "[%s, %s%s]",
			arm_regnames[RNFLD], UFLD?"":"-", arm_regnames[RMFLD]);
		if (WFLD)
			buf += sprintf(buf, "!");
	}
	else {
		buf += sprintf(buf, "[%s], %s%s",
			arm_regnames[RNFLD], UFLD?"":"-", arm_regnames[RMFLD]);
	}
	buf += sprintf(buf, ";\n");
	return buf;
}

static char *disasm_qadd(arm_inst_t inst, arm_addr_t addr, char *buf)
{
	buf += sprintf(buf, "qadd%s %s, %s, %s\n",
		arm_conditional[COND], arm_regnames[RDFLD],
		arm_regnames[RMFLD], arm_regnames[RNFLD]);
	return buf;
}

static char *disasm_qdadd(arm_inst_t inst, arm_addr_t addr, char *buf)
{
	buf += sprintf(buf, "qdadd%s %s, %s, %s\n",
		arm_conditional[COND], arm_regnames[RDFLD],
		arm_regnames[RMFLD], arm_regnames[RNFLD]);
	return buf;
}

static char *disasm_qsub(arm_inst_t inst, arm_addr_t addr, char *buf)
{
	buf += sprintf(buf, "qsub%s %s, %s, %s\n",
		arm_conditional[COND], arm_regnames[RDFLD],
		arm_regnames[RMFLD], arm_regnames[RNFLD]);
	return buf;
}

static char *disasm_qdsub(arm_inst_t inst, arm_addr_t addr, char *buf)
{
	buf += sprintf(buf, "qdsub%s %s, %s, %s\n",
		arm_conditional[COND], arm_regnames[RDFLD],
		arm_regnames[RMFLD], arm_regnames[RNFLD]);
	return buf;
}

#define XFLD ((inst>>5)&1)
#define YFLD ((inst>>6)&1)

static char *disasm_smla_xy(arm_inst_t inst, arm_addr_t addr, char *buf)
{
	buf += sprintf(buf, "smla%s%s%s %s, %s, %s, %s\n", XFLD?"t":"b",
		YFLD?"t":"b", arm_conditional[COND], arm_regnames[RNFLD],
		arm_regnames[RMFLD], arm_regnames[RSFLD], arm_regnames[RDFLD] );
	return buf;
}

static char *disasm_smlal_xy(arm_inst_t inst, arm_addr_t addr, char *buf)
{
	buf += sprintf(buf, "smlal%s%s%s %s, %s, %s, %s\n", XFLD?"t":"b",
		YFLD?"t":"b", arm_conditional[COND], arm_regnames[RDFLD],
		arm_regnames[RNFLD], arm_regnames[RMFLD], arm_regnames[RSFLD] );
	return buf;
}

static char *disasm_smlaw_y(arm_inst_t inst, arm_addr_t addr, char *buf)
{
	buf += sprintf(buf, "smlaw%s%s %s, %s, %s, %s\n", YFLD?"t":"b",
		arm_conditional[COND], arm_regnames[RNFLD],arm_regnames[RMFLD],
		arm_regnames[RSFLD], arm_regnames[RDFLD] );
	return buf;
}

static char *disasm_smul_xy(arm_inst_t inst, arm_addr_t addr, char *buf)
{
	buf += sprintf(buf, "smul%s%s%s %s, %s, %s\n", XFLD?"t":"b",
		YFLD?"t":"b", arm_conditional[COND], arm_regnames[RNFLD],
		arm_regnames[RMFLD], arm_regnames[RSFLD] );
	return buf;
}

static char *disasm_smulw_y(arm_inst_t inst, arm_addr_t addr, char *buf)
{
	buf += sprintf(buf, "smulw%s%s %s, %s, %s\n", YFLD?"t":"b",
		arm_conditional[COND], arm_regnames[RNFLD],
		arm_regnames[RMFLD], arm_regnames[RSFLD] );
	return buf;
}


#include "auto_disasm.h"
#include "arm_dec2.h"


char *arm_disassemble(arm_inst_t inst, arm_addr_t pc, char *buf)
{
	return disasm_main(inst, pc, buf);
}

void arm_disassemble_to_stream(arm_inst_t inst, arm_addr_t pc, FILE *stream)
{
	char buf[256];
	arm_disassemble(inst, pc, buf);
	fprintf(stream, "0x%08x : 0x%08x    %s", pc, inst, buf);
}

int arm_decode_regname(const char *name)
{
	for (int ii = 0; ii < 16; ii++)
		if (strcasecmp(name, arm_regnames_simple[ii]) == 0) return ii;

	for (int ii = 10; ii < 16; ii++)
		if (strcasecmp(name, arm_regnames[ii]) == 0) return ii;

	return -1;
}