📄 img_median_3x3_c.asm
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;*
;* Minimum safe trip count : 3
;*----------------------------------------------------------------------------*
;* SETUP CODE
;*
;* MV A6,B6
;* MV A8,B7
;* MV A9,B9
;*
;* SINGLE SCHEDULED ITERATION
;*
;* C60:
;* 0 LDBU .D1T1 *++A10,A4 ; |38|
;* 1 NOP 2
;* 3 LDBU .D2T2 *++B5,B10 ; |38|
;* 4 NOP 4
;* 8 LDBU .D1T1 *++A11,A4 ; |32|
;* 9 MV .L1 A4,A13 ; |38|
;* 10 CMPGT .L2X B10,A4,B0
;* 11 NOP 1
;* 12 [ B0] MV .S1X B10,A13 ; |39|
;* || [ B0] MV .S2X A4,B10 ; |39|
;* || CMPLT .L2 B9,B6,B2
;* 13 MV .S2X A4,B0 ; |32| Define a twin register
;* || MV .S1 A13,A0 ; |41|
;* || [ B2] MV .D2 B9,B6 ; |47| Define a twin register
;* 14 CMPGT .L2X A13,B0,B0
;* 15 MV .S1 A4,A5 ; |41|
;* 16 [ B0] MV .S1 A0,A5 ; |42|
;* || [ B0] MV .L1 A4,A0 ; |42|
;* 17 CMPGT .L2X B10,A0,B1
;* || MV .L1 A0,A3 ; |44|
;* 18 MV .D2 B10,B3 ; |44| ^
;* || CMPLT .L2X A5,B6,B0
;* 19 [ B1] MV .S1X B3,A3 ; |45| ^
;* || [ B1] MV .S2X A0,B3 ; |45|
;* || CMPGT .L2 B4,B8,B1
;* || [ A2] SUB .D1 A2,1,A2 ; |92|
;* 20 [ B2] MV .L1 A9,A6 ; |47|
;* || [ B1] MV .D2 B4,B8 ; |50|
;* || MV .S1 A3,A15 ; |55| ^
;* 21 [ B0] MV .L1 A5,A6 ; |48|
;* || MV .S1 A8,A0 ; |56|
;* || CMPGT .L2X A15,B7,B0 ; ^
;* 22 CMPGT .L2 B3,B8,B0
;* || [ B0] MV .S1 A0,A15 ; |59| ^
;* || [ B0] MV .D1 A3,A0 ; |60| ^
;* || MV .S2X A3,B7 ; |88|
;* 23 [ B0] MV .S2 B3,B8 ; |51|
;* || CMPGT .L1 A0,A7,A1 ; ^
;* || MV .D1 A6,A14 ; |73|
;* || MV .D2 B9,B6 ; |84|
;* 24 [ A1] MV .L1 A7,A0 ; |65| ^
;* || MV .S1 A8,A7 ; |85| Define a twin register
;* || MV .S2X A5,B9 ; |87|
;* || MV .D1 A3,A8 ; |88| Define a twin register
;* 25 MV .D1 A0,A3 ; |68| ^
;* || CMPGT .L1 A15,A0,A1 ; ^
;* 26 [ A1] MV .L1 A15,A3 ; |69| ^
;* 27 MV .D1 A3,A13 ; |73| ^
;* || CMPGT .L1 A6,A3,A1 ; ^
;* || MV .S1 A9,A6 ; |84| Define a twin register
;* 28 [ A1] MV .D1 A14,A13 ; |74| ^
;* || MV .L1 A5,A9 ; |87| Define a twin register
;* || [ A2] B .S2 C60 ; |92|
;* 29 CMPGT .L2X A13,B8,B0 ; ^
;* 30 [ A1] MV .D1 A3,A14 ; |74|
;* || [ B0] MV .S1X B8,A13 ; |77| ^
;* || MV .D2 B4,B8 ; |86| ^
;* 31 CMPGT .L1 A14,A13,A1
;* || MV .S2 B3,B4 ; |89| ^
;* 32 [ A1] MV .L1 A14,A13 ; |80|
;* 33 STB .D1T1 A13,*A12++ ; |91|
;* ; BRANCH OCCURS ; |92|
;*----------------------------------------------------------------------------*
L3: ; PIPED LOOP PROLOG
LDBU .D1T1 *++A11,A4 ; |32| (P) <0,8>
MV .S2X A9,B9
|| MV .D1 A4,A13 ; |38| (P) <0,9>
SUB .S1X B0,3,A2
|| CMPGT .L2X B10,A4,B0 ; (P) <0,10>
MV .S2X A6,B6
[ B0] MV .S1X B10,A13 ; |39| (P) <0,12>
|| [ B0] MV .S2X A4,B10 ; |39| (P) <0,12>
|| CMPLT .L2 B9,B6,B2 ; (P) <0,12>
[ B2] MV .D2 B9,B6 ; |47| (P) <0,13> Define a twin register
|| MV .S1 A13,A0 ; |41| (P) <0,13>
|| MV .S2X A4,B7 ; |32| (P) <0,13> Define a twin register
|| LDBU .D1T1 *++A10,A4 ; |38| (P) <1,0>
CMPGT .L2X A13,B7,B0 ; (P) <0,14>
MV .D1 A4,A5 ; |41| (P) <0,15>
[ B0] MV .D1 A0,A5 ; |42| (P) <0,16>
|| [ B0] MV .S1 A4,A0 ; |42| (P) <0,16>
|| LDBU .D2T2 *++B5,B10 ; |38| (P) <1,3>
MV .D1 A0,A3 ; |44| (P) <0,17>
|| CMPGT .L2X B10,A0,B1 ; (P) <0,17>
MV .D2 B10,B3 ; |44| (P) <0,18> ^
|| CMPLT .L2X A5,B6,B0 ; (P) <0,18>
[ B1] MV .S2X A0,B3 ; |45| (P) <0,19>
|| [ B1] MV .S1X B3,A3 ; |45| (P) <0,19> ^
|| CMPGT .L2 B4,B8,B1 ; (P) <0,19>
MV .S2X A8,B7
|| [ B1] MV .D2 B4,B8 ; |50| (P) <0,20>
|| [ B2] MV .D1 A9,A6 ; |47| (P) <0,20>
|| MV .S1 A3,A15 ; |55| (P) <0,20> ^
;** --------------------------------------------------------------------------*
L4: ; PIPED LOOP KERNEL
MV .S1 A8,A0 ; |56| <0,21>
|| CMPGT .L2X A15,B7,B0 ; <0,21> ^
|| [ B0] MV .L1 A5,A6 ; |48| <0,21>
|| LDBU .D1T1 *++A11,A4 ; |32| <1,8>
MV .S2X A3,B7 ; |88| <0,22>
|| CMPGT .L2 B3,B8,B0 ; <0,22>
|| [ B0] MV .D1 A3,A0 ; |60| <0,22> ^
|| [ B0] MV .S1 A0,A15 ; |59| <0,22> ^
|| MV .L1 A4,A13 ; |38| <1,9>
MV .D2 B9,B6 ; |84| <0,23>
|| [ B0] MV .S2 B3,B8 ; |51| <0,23>
|| MV .D1 A6,A14 ; |73| <0,23>
|| CMPGT .L1 A0,A7,A1 ; <0,23> ^
|| CMPGT .L2X B10,A4,B0 ; <1,10>
MV .D1 A3,A8 ; |88| <0,24> Define a twin register
|| MV .S1 A8,A7 ; |85| <0,24> Define a twin register
|| MV .S2X A5,B9 ; |87| <0,24>
|| [ A1] MV .L1 A7,A0 ; |65| <0,24> ^
CMPGT .L1 A15,A0,A1 ; <0,25> ^
|| MV .D1 A0,A3 ; |68| <0,25> ^
|| CMPLT .L2 B9,B6,B2 ; <1,12>
|| [ B0] MV .S1X B10,A13 ; |39| <1,12>
|| [ B0] MV .S2X A4,B10 ; |39| <1,12>
[ A1] MV .L1 A15,A3 ; |69| <0,26> ^
|| [ B2] MV .D2 B9,B6 ; |47| <1,13> Define a twin register
|| MV .S1 A13,A0 ; |41| <1,13>
|| MV .S2X A4,B0 ; |32| <1,13> Define a twin register
|| LDBU .D1T1 *++A10,A4 ; |38| <2,0>
MV .D1 A3,A13 ; |73| <0,27> ^
|| CMPGT .L1 A6,A3,A1 ; <0,27> ^
|| MV .S1 A9,A6 ; |84| <0,27> Define a twin register
|| CMPGT .L2X A13,B0,B0 ; <1,14>
[ A2] B .S2 L4 ; |92| <0,28>
|| [ A1] MV .D1 A14,A13 ; |74| <0,28> ^
|| MV .L1 A5,A9 ; |87| <0,28> Define a twin register
|| MV .S1 A4,A5 ; |41| <1,15>
CMPGT .L2X A13,B8,B0 ; <0,29> ^
|| [ B0] MV .S1 A0,A5 ; |42| <1,16>
|| [ B0] MV .L1 A4,A0 ; |42| <1,16>
|| LDBU .D2T2 *++B5,B10 ; |38| <2,3>
[ A1] MV .D1 A3,A14 ; |74| <0,30>
|| MV .D2 B4,B8 ; |86| <0,30> ^
|| [ B0] MV .S1X B8,A13 ; |77| <0,30> ^
|| MV .L1 A0,A3 ; |44| <1,17>
|| CMPGT .L2X B10,A0,B1 ; <1,17>
CMPGT .L1 A14,A13,A1 ; <0,31>
|| MV .S2 B3,B4 ; |89| <0,31> ^
|| CMPLT .L2X A5,B6,B0 ; <1,18>
|| MV .D2 B10,B3 ; |44| <1,18> ^
[ A1] MV .L1 A14,A13 ; |80| <0,32>
|| [ A2] SUB .D1 A2,1,A2 ; |92| <1,19>
|| [ B1] MV .S2X A0,B3 ; |45| <1,19>
|| CMPGT .L2 B4,B8,B1 ; <1,19>
|| [ B1] MV .S1X B3,A3 ; |45| <1,19> ^
STB .D1T1 A13,*A12++ ; |91| <0,33>
|| [ B1] MV .D2 B4,B8 ; |50| <1,20>
|| MV .S1 A3,A15 ; |55| <1,20> ^
|| [ B2] MV .L1 A9,A6 ; |47| <1,20>
;** --------------------------------------------------------------------------*
L5: ; PIPED LOOP EPILOG
MV .S1 A8,A0 ; |56| (E) <1,21>
|| [ B0] MV .L1 A5,A6 ; |48| (E) <1,21>
|| LDBU .D1T1 *++A11,A4 ; |32| (E) <2,8>
|| CMPGT .L2X A15,B7,B0 ; (E) <1,21> ^
MV .S2X A3,B7 ; |88| (E) <1,22>
|| [ B0] MV .D1 A3,A0 ; |60| (E) <1,22> ^
|| [ B0] MV .S1 A0,A15 ; |59| (E) <1,22> ^
|| MV .L1 A4,A13 ; |38| (E) <2,9>
|| CMPGT .L2 B3,B8,B0 ; (E) <1,22>
MV .D2 B9,B6 ; |84| (E) <1,23>
|| [ B0] MV .S2 B3,B8 ; |51| (E) <1,23>
|| MV .D1 A6,A14 ; |73| (E) <1,23>
|| CMPGT .L2X B10,A4,B0 ; (E) <2,10>
|| CMPGT .L1 A0,A7,A1 ; (E) <1,23> ^
MV .D1 A3,A8 ; |88| (E) <1,24> Define a twin register
|| MV .S1 A8,A7 ; |85| (E) <1,24> Define a twin register
|| [ A1] MV .L1 A7,A0 ; |65| (E) <1,24> ^
|| MV .S2X A5,B9 ; |87| (E) <1,24>
CMPGT .L1 A15,A0,A1 ; (E) <1,25> ^
|| MV .D1 A0,A3 ; |68| (E) <1,25> ^
|| [ B0] MV .S1X B10,A13 ; |39| (E) <2,12>
|| [ B0] MV .S2X A4,B10 ; |39| (E) <2,12>
|| CMPLT .L2 B9,B6,B2 ; (E) <2,12>
;** --------------------------------------------------------------------------*
MVC .S2 B11,CSR ; interrupts on
|| [ B2] MV .D2 B9,B6 ; |47| (E) <2,13> Define a twin register
|| MV .D1 A13,A0 ; |41| (E) <2,13>
|| MV .L2X A4,B5 ; |32| (E) <2,13> Define a twin register
|| [ A1] MV .S1 A15,A3 ; |69| (E) <1,26> ^
MV .D1 A3,A13 ; |73| (E) <1,27> ^
|| CMPGT .L2X A13,B5,B0 ; (E) <2,14>
|| MV .S1 A9,A6 ; |84| (E) <1,27> Define a twin register
|| CMPGT .L1 A6,A3,A1 ; (E) <1,27> ^
[ A1] MV .D1 A14,A13 ; |74| (E) <1,28> ^
|| MV .S1 A4,A5 ; |41| (E) <2,15>
|| [ B2] MV .L1 A5,A6 ; |87|
[ A1] MV .D1 A3,A14 ; |74| (E) <1,30>
|| CMPGT .L2X A13,B8,B0 ; (E) <1,29> ^
|| [ B0] MV .S1 A4,A0 ; |42| (E) <2,16>
|| [ B0] MV .L1 A0,A5 ; |42| (E) <2,16>
MV .D1 A0,A3 ; |44| (E) <2,17>
|| CMPGT .L2X B10,A0,B1 ; (E) <2,17>
|| MV .D2 B3,B4 ; |89| (E) <1,31> ^
|| MV .S2 B4,B8 ; |86| (E) <1,30> ^
|| [ B0] MV .S1X B8,A13 ; |77| (E) <1,30> ^
CMPGT .L1 A14,A13,A1 ; (E) <1,31>
|| [ B1] MV .S1X B10,A3 ; |44|
|| MV .D2 B10,B3 ; |44|
|| CMPLT .L2X A5,B6,B0 ; (E) <2,18>
CMPGT .L2 B4,B8,B1 ; (E) <2,19>
|| [ A1] MV .D1 A14,A13 ; |80| (E) <1,32>
|| MV .S1 A8,A0 ; |56|
|| [ B0] MV .L1 A5,A6 ; |48| (E) <2,21>
|| [ B1] MV .S2X A0,B3 ; |45| (E) <2,19>
MV .S1 A6,A14 ; |73|
|| STB .D1T1 A13,*A12++ ; |91| (E) <1,33>
|| [ B1] MV .D2 B4,B8 ; |50| (E) <2,20>
|| MV .L1 A3,A15 ; |55|
|| CMPGT .L2X A3,B7,B0
CMPGT .L2 B3,B8,B0 ; (E) <2,22>
|| [ B0] MV .D1 A8,A15 ; |56|
|| [ B0] MV .S1 A3,A0 ; |60| (E) <2,22> ^
[ B0] MV .D2 B3,B8 ; |51| (E) <2,23>
|| CMPGT .L1 A0,A7,A1 ; (E) <2,23> ^
[ A1] MV .D1 A7,A0 ; |65| (E) <2,24> ^
MV .D1 A0,A3 ; |68| (E) <2,25> ^
|| CMPGT .L1 A15,A0,A1 ; (E) <2,25> ^
[ A1] MV .D1 A15,A3 ; |69| (E) <2,26> ^
MV .D1 A3,A13 ; |73| (E) <2,27> ^
|| CMPGT .L1 A6,A3,A1 ; (E) <2,27> ^
[ A1] MV .D1 A3,A14 ; |74| (E) <2,30>
|| [ A1] MV .S1 A6,A13 ; |73|
CMPGT .L2X A13,B8,B0 ; (E) <2,29> ^
[ B0] MV .S1X B8,A13 ; |77| (E) <2,30> ^
CMPGT .L1 A14,A13,A1 ; (E) <2,31>
[ A1] MV .D1 A14,A13 ; |80| (E) <2,32>
STB .D1T1 A13,*A12++ ; |91| (E) <2,33>
;** --------------------------------------------------------------------------*
L6:
.line 87
LDW .D2T2 *+SP(28),B3 ; |93|
LDW .D2T1 *+SP(12),A11 ; |93|
LDW .D2T1 *+SP(8),A10 ; |93|
|| MV .S1X SP,A9 ; |93|
LDW .D1T1 *+A9(20),A13 ; |93|
LDW .D1T1 *+A9(16),A12 ; |93|
|| LDW .D2T2 *+SP(32),B10 ; |93|
RET .S2 B3 ; |93|
|| LDW .D1T1 *+A9(24),A14 ; |93|
|| LDW .D2T2 *+SP(36),B11 ; |93|
LDW .D2T1 *++SP(40),A15 ; |93|
NOP 4
; BRANCH OCCURS ; |93|
.endfunc 93,00c08fc00h,40
;******************************************************************************
;* TYPE INFORMATION *
;******************************************************************************
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