📄 median_3x3.asm
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;******************************************************************************
;* TMS320C6x C/C++ Codegen PC Version 4.32 *
;* Date/Time created: Mon Mar 13 18:11:55 2006 *
;******************************************************************************
;******************************************************************************
;* GLOBAL FILE PARAMETERS *
;* *
;* Architecture : TMS320C620x *
;* Optimization : Enabled at level 3 *
;* Optimizing for : Speed *
;* Based on options: -o3, no -ms *
;* Endian : Little *
;* Interrupt Thrshld : Disabled *
;* Memory Model : Small *
;* Calls to RTS : Near *
;* Pipelining : Enabled *
;* Speculative Load : Disabled *
;* Memory Aliases : Presume are aliases (pessimistic) *
;* Debug Info : COFF Debug *
;* *
;******************************************************************************
.asg A15, FP
.asg B14, DP
.asg B15, SP
.global $bss
.file "median_3x3.c"
; c:\ti\c6000\cgtools\bin\opt6x.exe -O3 C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp\TI980_2 C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp\TI980_5 -w D:/TIDSPtraining/5thday/src/media_33/Debug
.sect ".text"
.global _median_3x3
.sym _median_3x3,_median_3x3, 32, 2, 0
.func 4
;******************************************************************************
;* FUNCTION NAME: _median_3x3 *
;* *
;* Regs Modified : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,B0,B1,B4,B5,B6,*
;* B7,B8,B9,SP *
;* Regs Used : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,B0,B1,B3,B4,B5,*
;* B6,B7,B8,B9,DP,SP *
;* Local Frame Size : 0 Args + 12 Auto + 8 Save = 20 byte *
;******************************************************************************
;******************************************************************************
;* *
;* Using -g (debug) with optimization (-o3) may disable key optimizations! *
;* *
;******************************************************************************
_median_3x3:
;** --------------------------------------------------------------------------*
.line 2
.sym _in_data,4, 28, 17, 32
.sym _cols,20, 4, 17, 32
.sym _out_data,6, 28, 17, 32
.sym _out_data,0, 28, 4, 32
.sym _cols,20, 4, 4, 32
.sym _in_data,5, 28, 4, 32
.sym _out_data,25, 28, 4, 32
.sym _line1,9, 28, 4, 32
.sym _line2,17, 28, 4, 32
.sym _i,6, 4, 4, 32
.sym _k,7, 4, 4, 32
.sym _temp1,0, 12, 4, 8
.sym _temp,4, 60, 1, 72,, 9
STW .D2T1 A11,*SP--(24) ; |5|
STW .D2T1 A10,*+SP(20) ; |5|
MV .D1 A4,A5 ; |5|
|| MV .S2X A6,B9 ; |5|
.line 6
ADD .S1X B4,A5,A9 ; |9|
.line 7
ADD .D2 B4,B4,B5 ; |10|
ADD .S2X B5,A5,B1 ; |10|
.line 9
CMPGT .L2 B4,2,B0 ; |12|
[!B0] B .S1 L6 ; |12|
ZERO .D1 A6 ; |12|
ADD .D1 2,A5,A10
ADD .S1X B5,A5,A8
ADD .L1 1,A5,A11
ADD .S2X B4,A5,B8
|| SUB .D2 B4,2,B7
; BRANCH OCCURS ; |12|
;** --------------------------------------------------------------------------*
;** BEGIN LOOP L1
;** --------------------------------------------------------------------------*
L1:
.line 13
LDBU .D1T1 *A5,A0 ; |16|
NOP 4
ADD .D1 A6,A0,A0 ; |16|
STB .D2T1 A0,*+SP(4) ; |16|
.line 14
LDBU .D1T2 *+A6[A11],B4 ; |17|
NOP 4
STB .D2T2 B4,*+SP(5) ; |17|
.line 15
LDBU .D1T1 *+A6[A10],A0 ; |18|
NOP 4
STB .D2T1 A0,*+SP(6) ; |18|
.line 16
LDBU .D1T1 *A9,A0 ; |19|
NOP 4
ADD .D1 A6,A0,A0 ; |19|
STB .D2T1 A0,*+SP(7) ; |19|
.line 17
LDBU .D2T2 *++B8,B4 ; |20|
NOP 4
STB .D2T2 B4,*+SP(8) ; |20|
.line 18
LDBU .D2T2 *+B8(1),B4 ; |21|
NOP 4
STB .D2T2 B4,*+SP(9) ; |21|
.line 19
LDBU .D2T2 *B1,B4 ; |22|
NOP 4
ADD .S2X A6,B4,B4 ; |22|
STB .D2T2 B4,*+SP(10) ; |22|
.line 20
LDBU .D1T1 *++A8,A0 ; |23|
NOP 4
STB .D2T1 A0,*+SP(11) ; |23|
.line 21
LDBU .D1T1 *+A8(1),A0 ; |24|
NOP 4
STB .D2T1 A0,*+SP(12) ; |24|
.line 24
MVK .S2 0x5,B0 ; |27|
|| ZERO .D1 A7 ; |27|
;** --------------------------------------------------------------------------*
;** BEGIN LOOP L2
;** --------------------------------------------------------------------------*
L2:
.line 28
MVC .S2 CSR,B6
AND .S2 -2,B6,B5
ADD .S1X 4,SP,A3
|| MVC .S2 B5,CSR ; interrupts off
;*----------------------------------------------------------------------------*
;* SOFTWARE PIPELINE INFORMATION
;*
;* Loop source line : 29
;* Loop opening brace source line : 30
;* Loop closing brace source line : 37
;* Known Minimum Trip Count : 4
;* Known Maximum Trip Count : 8
;* Known Max Trip Count Factor : 1
;* Loop Carried Dependency Bound(^) : 7
;* Unpartitioned Resource Bound : 2
;* Partitioned Resource Bound(*) : 2
;* Resource Partition:
;* A-side B-side
;* .L units 1 0
;* .S units 1 0
;* .D units 2* 2*
;* .M units 0 0
;* .X cross paths 0 2*
;* .T address paths 2* 2*
;* Long read paths 0 2*
;* Long write paths 0 0
;* Logical ops (.LS) 0 2 (.L or .S unit)
;* Addition ops (.LSD) 1 1 (.L or .S or .D unit)
;* Bound(.L .S .LS) 1 1
;* Bound(.L .S .D .LS .LSD) 2* 2*
;*
;* Searching for software pipeline schedule at ...
;* ii = 7 Schedule found with 2 iterations in parallel
;*
;* Register Usage Table:
;* +---------------------------------+
;* |AAAAAAAAAAAAAAAA|BBBBBBBBBBBBBBBB|
;* |0000000000111111|0000000000111111|
;* |0123456789012345|0123456789012345|
;* |----------------+----------------|
;* 0: | ** | * |
;* 1: | ** | * |
;* 2: | ** | * |
;* 3: |* ** | * |
;* 4: |* *** | * |
;* 5: |**** | ** |
;* 6: | *** | ** |
;* +---------------------------------+
;*
;* Done
;*
;* Epilog not removed
;* Collapsed epilog stages : 0
;*
;* Prolog not removed
;* Collapsed prolog stages : 0
;*
;* Minimum required memory pad : 0 bytes
;*
;* Minimum safe trip count : 2
;*----------------------------------------------------------------------------*
;* SETUP CODE
;*
;* MV A3,B4
;*
;* SINGLE SCHEDULED ITERATION
;*
;* C26:
;* 0 LDBU .D1T1 *++A3,A0
;* 1 LDBU .D1T1 *-A3(1),A4 ; ^
;* 2 [ A2] SUB .D1 A2,1,A2 ; |37|
;* 3 [ A2] B .S1 C26 ; |37|
;* 4 NOP 2
;* 6 CMPGT .L1 A4,A0,A1 ; ^
;* || MV .S2X A4,B5 ; |33| ^
;* || ADD .D2 1,B4,B4 ; |33|
;* 7 MV .S2X A0,B5 ; Define a twin register
;* || [ A1] STB .D2T2 B5,*B4 ; |35| ^
;* 8 [ A1] STB .D2T2 B5,*-B4(1) ; |34|
;* ; BRANCH OCCURS ; |37|
;*----------------------------------------------------------------------------*
L3: ; PIPED LOOP PROLOG
SUB .S1 8,A7,A0 ; |31|
|| LDBU .D1T1 *++A3,A0 ; (P) <0,0>
ADD .D2 4,SP,B4
|| SUB .S1 A0,1,A2
|| LDBU .D1T1 *-A3(1),A4 ; (P) <0,1> ^
;** --------------------------------------------------------------------------*
L4: ; PIPED LOOP KERNEL
[ A2] SUB .D1 A2,1,A2 ; |37| <0,2>
[ A2] B .S1 L4 ; |37| <0,3>
NOP 2
ADD .D2 1,B4,B4 ; |33| <0,6>
|| MV .S2X A4,B5 ; |33| <0,6> ^
|| CMPGT .L1 A4,A0,A1 ; <0,6> ^
MV .S2X A0,B5 ; <0,7> Define a twin register
|| [ A1] STB .D2T2 B5,*B4 ; |35| <0,7> ^
|| LDBU .D1T1 *++A3,A0 ; <1,0>
[ A1] STB .D2T2 B5,*-B4(1) ; |34| <0,8>
|| LDBU .D1T1 *-A3(1),A4 ; <1,1> ^
;** --------------------------------------------------------------------------*
L5: ; PIPED LOOP EPILOG
;** --------------------------------------------------------------------------*
ADD .D2 1,B4,B4 ; |33| (E) <1,6>
NOP 2
MVC .S2 B6,CSR ; interrupts on
MV .S2X A4,B5 ; |33| (E) <1,6> ^
|| CMPGT .L1 A4,A0,A1 ; (E) <1,6> ^
MV .S2X A0,B5 ; (E) <1,7> Define a twin register
|| [ A1] STB .D2T2 B5,*B4 ; |35| (E) <1,7> ^
[ A1] STB .D2T2 B5,*-B4(1) ; |34| (E) <1,8>
.line 35
ADD .D1 1,A7,A7 ; |38|
|| SUB .D2 B0,1,B0 ; |38|
[ B0] B .S2 L2 ; |38|
NOP 5
; BRANCH OCCURS ; |38|
;** --------------------------------------------------------------------------*
.line 36
LDBU .D2T2 *+SP(8),B4 ; |39|
NOP 4
STB .D2T2 B4,*B9++ ; |39|
.line 37
SUB .S1X B7,1,A1 ; |40|
[ A1] B .S1 L1 ; |40|
SUB .D2 B7,1,B7 ; |40|
ADD .D1 1,A6,A6 ; |40|
NOP 3
; BRANCH OCCURS ; |40|
;** --------------------------------------------------------------------------*
L6:
.line 38
RET .S2 B3 ; |41|
|| LDW .D2T1 *+SP(20),A10 ; |41|
LDW .D2T1 *++SP(24),A11 ; |41|
NOP 4
; BRANCH OCCURS ; |41|
.endfunc 41,000000c00h,24
;******************************************************************************
;* TYPE INFORMATION *
;******************************************************************************
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