📄 vga.c
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#include "iic.h"
#include "bootpara.h"
void _Delay(int time)
{
volatile int i, j;
for (i = 0; i < time * 512; i++)
j = i;
}
//**********************[IicPoll ]**************************************
void _IicPoll(void)
{
U32 iicSt,i;
iicSt = rIICSTAT;
if(iicSt & 0x8){} //When bus arbitration is failed.
if(iicSt & 0x4){} //When a slave address is matched with IICADD
if(iicSt & 0x2){} //When a slave address is 0000000b
if(iicSt & 0x1){} //When ACK isn't received
switch(__iicMode)
{
case POLLACK:
__iicStatus = iicSt;
break;
case RDDATA:
if((__iicDataCount--)==0)
{
__iicData[__iicPt++] = rIICDS;
rIICSTAT = 0x90; //Stop MasRx condition
rIICCON = 0xaf; //Resumes IIC operation.
_Delay(1); //Wait until stop condtion is in effect.
//Too long time...
//The pending bit will not be set after issuing stop condition.
break;
}
__iicData[__iicPt++] = rIICDS;
//The last data has to be read with no ack.
if((__iicDataCount)==0)
rIICCON = 0x2f; //Resumes IIC operation with NOACK.
else
rIICCON = 0xaf; //Resumes IIC operation with ACK
break;
case WRDATA:
if((__iicDataCount--)==0)
{
rIICSTAT = 0xd0; //stop MasTx condition
rIICCON = 0xaf; //resumes IIC operation.
_Delay(1); //wait until stop condtion is in effect.
//The pending bit will not be set after issuing stop condition.
break;
}
rIICDS = __iicData[__iicPt++]; //_iicData[0] has dummy.
for(i=0;i<10;i++); //for setup time until rising edge of IICSCL
rIICCON = 0xaf; //resumes IIC operation.
break;
case SETRDADDR:
// printk("[S%d]",_iicDataCount);
if((__iicDataCount--)==0)
{
break; //IIC operation is stopped because of IICCON[4]
}
rIICDS = __iicData[__iicPt++];
for(i=0;i<10;i++); //for setup time until rising edge of IICSCL
rIICCON = 0xaf; //resumes IIC operation.
break;
default:
break;
}
}
//**********************[ Run_IicPoll ]*********************************
void _Run_IicPoll(void)
{
if(rIICCON & 0x10) //Tx/Rx Interrupt Enable
_IicPoll();
}
void __Wr24C080(U32 slvAddr,U32 addr,U8 data)
{
int times = 0;
__iicMode = WRDATA;
__iicPt = 0;
__iicData[0] = (U8)addr;
__iicData[1] = data;
__iicDataCount = 2;
if (__iic_error)
return;
rIICDS = slvAddr; //0xa0
//Master Tx mode, Start(Write), IIC-bus data output enable
//Bus arbitration sucessful, Address as slave status flag Cleared,
//Address zero status flag cleared, Last received bit is 0
rIICSTAT = 0xf0;
//Clearing the pending bit isn't needed because the pending bit has been cleared.
while(__iicDataCount!=-1)
_Run_IicPoll();
__iicMode = POLLACK;
while(1)
{
rIICDS = slvAddr;
__iicStatus = 0x100; //To check if _iicStatus is changed
rIICSTAT = 0xf0; //Master Tx, Start, Output Enable, Sucessful, Cleared, Cleared, 0
rIICCON = 0xaf; //Resumes IIC operation.
while(__iicStatus==0x100 && times++ < 512)
_Run_IicPoll();
if (times > 512)
__iic_error = 1;
if(!(__iicStatus & 0x1) || __iic_error)
break; //When ACK is received
}
rIICSTAT = 0xd0; //Master Tx condition, Stop(Write), Output Enable
rIICCON = 0xaf; //Resumes IIC operation.
_Delay(1); //Wait until stop condtion is in effect.
//Write is completed.
}
void display_format(int mode)
{
if(mode==2)
{
__Wr24C080(VGA_ADDR, 0x00, 0x61);
__Wr24C080(VGA_ADDR, 0x04, 0x00);
__Wr24C080(VGA_ADDR, 0x07, 0x64);
__Wr24C080(VGA_ADDR, 0x08, 0x01);
__Wr24C080(VGA_ADDR, 0x0a, 0x30);
__Wr24C080(VGA_ADDR, 0x0b, 0x20);
__Wr24C080(VGA_ADDR, 0x09, 0x69);
__Wr24C080(VGA_ADDR, 0x0e, 0x0a);
__Wr24C080(VGA_ADDR, 0x10, 0x00);
__Wr24C080(VGA_ADDR, 0x3d, 0x00);
__Wr24C080(VGA_ADDR, 0x01, 0x08);
__Wr24C080(VGA_ADDR, 0x1c, 0xe0);
__Wr24C080(VGA_ADDR, 0x20, 0x0a);
__Wr24C080(VGA_ADDR, 0x21, 0x01);
__Wr24C080(VGA_ADDR, 0x24, 0x01);
__Wr24C080(VGA_ADDR, 0x04, 0x00);
}
else
{
__Wr24C080(VGA_ADDR, 0x04, 0x20);
}
if (__iic_error == 0)
Uart_Printf(" |VGA init done! |\n");
else
Uart_Printf(" |VGA init unsuccessful!!! |\n");
}
int display_init()
{
//int ret;
unsigned value;
IICCON = ACK_ENA | CLK_512 | 0xf;
rGPEUP |= 0xc000; //Pull-up disable
rGPECON |= 0xa00000; //GPE15:IICSDA , GPE14:IICSCL
//Enable ACK, Prescaler IICCLK=PCLK/16, Enable interrupt, Transmit clock value Tx clock=IICCLK/16
rIICCON = (1<<7) | (0<<6) | (1<<5) | (0xf);
rIICADD = 0x10; //2410 slave address = [7:1]
rIICSTAT = 0x10; //IIC bus data output enable(Rx/Tx)
#if 1
BANKCON6=0x00018001; //TRCD=4 clocks /SDRAM
BANKCON7=0x00018001; //TRCD=4 clocks /SDRAM
//BANKCON6=0x00018001; //TRCD=2 clocks /SDRAM
//BANKCON7=0x00018001; //TRCD=2 clocks /SDRAM
REFRESH=0x008e01e9; //刷新时间为15.6us HCLK=@100M
MRSRB6=0x20; //CL=2HCLK
MRSRB7=0x20; //CL=2HCLK
#endif
value = 1;
if(boot_params.display_sel.val==2)value=2;//TV mode
__iic_error = 0;
display_format(value);
}
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