dds.tan.qmsg

基于DDS原理的正弦信号发生器。用VERILOG语言实现

{ "Info" "ITAN_NO_REG2REG_EXIST" "clk " "Info: No valid register-to-register data paths exist for clock \"clk\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "altpll0:inst1\|altpll:altpll_component\|_clk0 register DDS:inst\|add\[1\] register DDS:inst\|add\[1\] 1.148 ns " "Info: Minimum slack time is 1.148 ns for clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" between source register \"DDS:inst\|add\[1\]\" and destination register \"DDS:inst\|add\[1\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.150 ns + Shortest register register " "Info: + Shortest register to register delay is 1.150 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DDS:inst\|add\[1\] 1 REG LCFF_X57_Y25_N15 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X57_Y25_N15; Fanout = 2; REG Node = 'DDS:inst\|add\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DDS:inst|add[1] } "NODE_NAME" } } { "DDS.v" "" { Text "E:/DDS/DDS.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.427 ns) + CELL(0.615 ns) 1.042 ns DDS:inst\|add\[1\]~204 2 COMB LCCOMB_X57_Y25_N14 1 " "Info: 2: + IC(0.427 ns) + CELL(0.615 ns) = 1.042 ns; Loc. = LCCOMB_X57_Y25_N14; Fanout = 1; COMB Node = 'DDS:inst\|add\[1\]~204'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.042 ns" { DDS:inst|add[1] DDS:inst|add[1]~204 } "NODE_NAME" } } { "DDS.v" "" { Text "E:/DDS/DDS.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 1.150 ns DDS:inst\|add\[1\] 3 REG LCFF_X57_Y25_N15 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.150 ns; Loc. = LCFF_X57_Y25_N15; Fanout = 2; REG Node = 'DDS:inst\|add\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { DDS:inst|add[1]~204 DDS:inst|add[1] } "NODE_NAME" } } { "DDS.v" "" { Text "E:/DDS/DDS.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.723 ns ( 62.87 % ) " "Info: Total cell delay = 0.723 ns ( 62.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.427 ns ( 37.13 % ) " "Info: Total interconnect delay = 0.427 ns ( 37.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.150 ns" { DDS:inst|add[1] DDS:inst|add[1]~204 DDS:inst|add[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.150 ns" { DDS:inst|add[1] {} DDS:inst|add[1]~204 {} DDS:inst|add[1] {} } { 0.000ns 0.427ns 0.000ns } { 0.000ns 0.615ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.002 ns - Smallest register register " "Info: - Smallest register to register requirement is 0.002 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -2.804 ns " "Info: + Latch edge is -2.804 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination altpll0:inst1\|altpll:altpll_component\|_clk0 6.666 ns -2.804 ns  50 " "Info: Clock period of Destination clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" is 6.666 ns with  offset of -2.804 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.804 ns " "Info: - Launch edge is -2.804 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source altpll0:inst1\|altpll:altpll_component\|_clk0 6.666 ns -2.804 ns  50 " "Info: Clock period of Source clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" is 6.666 ns with  offset of -2.804 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst1\|altpll:altpll_component\|_clk0 destination 3.225 ns + Longest register " "Info: + Longest clock path from clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" to destination register is 3.225 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 2; CLK Node = 'altpll0:inst1\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.382 ns) + CELL(0.000 ns) 1.382 ns altpll0:inst1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G2 51 " "Info: 2: + IC(1.382 ns) + CELL(0.000 ns) = 1.382 ns; Loc. = CLKCTRL_G2; Fanout = 51; COMB Node = 'altpll0:inst1\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.382 ns" { altpll0:inst1|altpll:altpll_component|_clk0 altpll0:inst1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.177 ns) + CELL(0.666 ns) 3.225 ns DDS:inst\|add\[1\] 3 REG LCFF_X57_Y25_N15 2 " "Info: 3: + IC(1.177 ns) + CELL(0.666 ns) = 3.225 ns; Loc. = LCFF_X57_Y25_N15; Fanout = 2; REG Node = 'DDS:inst\|add\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.843 ns" { altpll0:inst1|altpll:altpll_component|_clk0~clkctrl DDS:inst|add[1] } "NODE_NAME" } } { "DDS.v" "" { Text "E:/DDS/DDS.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 20.65 % ) " "Info: Total cell delay = 0.666 ns ( 20.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.559 ns ( 79.35 % ) " "Info: Total interconnect delay = 2.559 ns ( 79.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.225 ns" { altpll0:inst1|altpll:altpll_component|_clk0 altpll0:inst1|altpll:altpll_component|_clk0~clkctrl DDS:inst|add[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.225 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} altpll0:inst1|altpll:altpll_component|_clk0~clkctrl {} DDS:inst|add[1] {} } { 0.000ns 1.382ns 1.177ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst1\|altpll:altpll_component\|_clk0 source 3.225 ns - Shortest register " "Info: - Shortest clock path from clock \"altpll0:inst1\|altpll:altpll_component\|_clk0\" to source register is 3.225 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 2; CLK Node = 'altpll0:inst1\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.382 ns) + CELL(0.000 ns) 1.382 ns altpll0:inst1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G2 51 " "Info: 2: + IC(1.382 ns) + CELL(0.000 ns) = 1.382 ns; Loc. = CLKCTRL_G2; Fanout = 51; COMB Node = 'altpll0:inst1\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.382 ns" { altpll0:inst1|altpll:altpll_component|_clk0 altpll0:inst1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.177 ns) + CELL(0.666 ns) 3.225 ns DDS:inst\|add\[1\] 3 REG LCFF_X57_Y25_N15 2 " "Info: 3: + IC(1.177 ns) + CELL(0.666 ns) = 3.225 ns; Loc. = LCFF_X57_Y25_N15; Fanout = 2; REG Node = 'DDS:inst\|add\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.843 ns" { altpll0:inst1|altpll:altpll_component|_clk0~clkctrl DDS:inst|add[1] } "NODE_NAME" } } { "DDS.v" "" { Text "E:/DDS/DDS.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 20.65 % ) " "Info: Total cell delay = 0.666 ns ( 20.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.559 ns ( 79.35 % ) " "Info: Total interconnect delay = 2.559 ns ( 79.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.225 ns" { altpll0:inst1|altpll:altpll_component|_clk0 altpll0:inst1|altpll:altpll_component|_clk0~clkctrl DDS:inst|add[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.225 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} altpll0:inst1|altpll:altpll_component|_clk0~clkctrl {} DDS:inst|add[1] {} } { 0.000ns 1.382ns 1.177ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.225 ns" { altpll0:inst1|altpll:altpll_component|_clk0 altpll0:inst1|altpll:altpll_component|_clk0~clkctrl DDS:inst|add[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.225 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} altpll0:inst1|altpll:altpll_component|_clk0~clkctrl {} DDS:inst|add[1] {} } { 0.000ns 1.382ns 1.177ns } { 0.000ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.225 ns" { altpll0:inst1|altpll:altpll_component|_clk0 altpll0:inst1|altpll:altpll_component|_clk0~clkctrl DDS:inst|add[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.225 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} altpll0:inst1|altpll:altpll_component|_clk0~clkctrl {} DDS:inst|add[1] {} } { 0.000ns 1.382ns 1.177ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" {  } { { "DDS.v" "" { Text "E:/DDS/DDS.v" 24 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "DDS.v" "" { Text "E:/DDS/DDS.v" 24 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.225 ns" { altpll0:inst1|altpll:altpll_component|_clk0 altpll0:inst1|altpll:altpll_component|_clk0~clkctrl DDS:inst|add[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.225 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} altpll0:inst1|altpll:altpll_component|_clk0~clkctrl {} DDS:inst|add[1] {} } { 0.000ns 1.382ns 1.177ns } { 0.000ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.225 ns" { altpll0:inst1|altpll:altpll_component|_clk0 altpll0:inst1|altpll:altpll_component|_clk0~clkctrl DDS:inst|add[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.225 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} altpll0:inst1|altpll:altpll_component|_clk0~clkctrl {} DDS:inst|add[1] {} } { 0.000ns 1.382ns 1.177ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.150 ns" { DDS:inst|add[1] DDS:inst|add[1]~204 DDS:inst|add[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.150 ns" { DDS:inst|add[1] {} DDS:inst|add[1]~204 {} DDS:inst|add[1] {} } { 0.000ns 0.427ns 0.000ns } { 0.000ns 0.615ns 0.108ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.225 ns" { altpll0:inst1|altpll:altpll_component|_clk0 altpll0:inst1|altpll:altpll_component|_clk0~clkctrl DDS:inst|add[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.225 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} altpll0:inst1|altpll:altpll_component|_clk0~clkctrl {} DDS:inst|add[1] {} } { 0.000ns 1.382ns 1.177ns } { 0.000ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.225 ns" { altpll0:inst1|altpll:altpll_component|_clk0 altpll0:inst1|altpll:altpll_component|_clk0~clkctrl DDS:inst|add[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.225 ns" { altpll0:inst1|altpll:altpll_component|_clk0 {} altpll0:inst1|altpll:altpll_component|_clk0~clkctrl {} DDS:inst|add[1] {} } { 0.000ns 1.382ns 1.177ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}