prev_cmp_dds.qmsg

基于DDS原理的正弦信号发生器。用VERILOG语言实现

{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0 "" 0}  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "33 unused 3.30 21 12 0 " "Info: Number of I/O pins in group: 33 (unused VREF, 3.30 VCCIO, 21 input, 12 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." {  } {  } 0 0 "I/O standards used: %1!s!" 0 0 "" 0}  } {  } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.30V 1 45 " "Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 1 total pin(s) used --  45 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 3 36 " "Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 3 total pin(s) used --  36 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 39 " "Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  39 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 36 " "Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  36 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 44 " "Info: I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  44 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 42 " "Info: I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  42 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 36 " "Info: I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  36 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 39 " "Info: I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  39 pins available" {  } {  } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "" 0}  } {  } 0 0 "Statistics of %1!s!" 0 0 "" 0}  } {  } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Info: Fitter placement operations ending: elapsed time is 00:00:03" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.538 ns register register " "Info: Estimated most critical path is register to register delay of 3.538 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DDS:inst\|add\[0\] 1 REG LAB_X12_Y6 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X12_Y6; Fanout = 2; REG Node = 'DDS:inst\|add\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DDS:inst|add[0] } "NODE_NAME" } } { "DDS.v" "" { Text "E:/DDS/DDS.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.648 ns) + CELL(0.621 ns) 1.269 ns DDS:inst\|add\[0\]~203 2 COMB LAB_X12_Y6 2 " "Info: 2: + IC(0.648 ns) + CELL(0.621 ns) = 1.269 ns; Loc. = LAB_X12_Y6; Fanout = 2; COMB Node = 'DDS:inst\|add\[0\]~203'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.269 ns" { DDS:inst|add[0] DDS:inst|add[0]~203 } "NODE_NAME" } } { "DDS.v" "" { Text "E:/DDS/DDS.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.355 ns DDS:inst\|add\[1\]~205 3 COMB LAB_X12_Y6 2 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.355 ns; Loc. = LAB_X12_Y6; Fanout = 2; COMB Node = 'DDS:inst\|add\[1\]~205'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { DDS:inst|add[0]~203 DDS:inst|add[1]~205 } "NODE_NAME" } } { "DDS.v" "" { Text "E:/DDS/DDS.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.441 ns DDS:inst\|add\[2\]~207 4 COMB LAB_X12_Y6 2 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.441 ns; Loc. = LAB_X12_Y6; Fanout = 2; COMB Node = 'DDS:inst\|add\[2\]~207'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { DDS:inst|add[1]~205 DDS:inst|add[2]~207 } "NODE_NAME" } } { "DDS.v" "" { Text "E:/DDS/DDS.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.527 ns DDS:inst\|add\[3\]~209 5 COMB LAB_X12_Y6 2 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 1.527 ns; Loc. = LAB_X12_Y6; Fanout = 2; COMB Node = 'DDS:inst\|add\[3\]~209'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { DDS:inst|add[2]~207 DDS:inst|add[3]~209 } "NODE_NAME" } } { "DDS.v" "" { Text "E:/DDS/DDS.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.613 ns DDS:inst\|add\[4\]~211 6 COMB LAB_X12_Y6 2 " "Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 1.613 ns; Loc. = LAB_X12_Y6; Fanout = 2; COMB Node = 'DDS:inst\|add\[4\]~211'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { DDS:inst|add[3]~209 DDS:inst|add[4]~211 } "NODE_NAME" } } { "DDS.v" "" { Text "E:/DDS/DDS.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.699 ns DDS:inst\|add\[5\]~213 7 COMB LAB_X12_Y6 2 " "Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 1.699 ns; Loc. = LAB_X12_Y6; Fanout = 2; COMB Node = 'DDS:inst\|add\[5\]~213'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { DDS:inst|add[4]~211 DDS:inst|add[5]~213 } "NODE_NAME" } } { "DDS.v" "" { Text "E:/DDS/DDS.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.785 ns DDS:inst\|add\[6\]~215 8 COMB LAB_X12_Y6 2 " "Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 1.785 ns; Loc. = LAB_X12_Y6; Fanout = 2; COMB Node = 'DDS:inst\|add\[6\]~215'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { DDS:inst|add[5]~213 DDS:inst|add[6]~215 } "NODE_NAME" } } { "DDS.v" "" { Text "E:/DDS/DDS.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.871 ns DDS:inst\|add\[7\]~217 9 COMB LAB_X12_Y6 2 " "Info: 9: + IC(0.000 ns) + CELL(0.086 ns) = 1.871 ns; Loc. = LAB_X12_Y6; Fanout = 2; COMB Node = 'DDS:inst\|add\[7\]~217'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { DDS:inst|add[6]~215 DDS:inst|add[7]~217 } "NODE_NAME" } } { "DDS.v" "" { Text "E:/DDS/DDS.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.957 ns DDS:inst\|add\[8\]~219 10 COMB LAB_X12_Y6 2 " "Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 1.957 ns; Loc. = LAB_X12_Y6; Fanout = 2; COMB Node = 'DDS:inst\|add\[8\]~219'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { DDS:inst|add[7]~217 DDS:inst|add[8]~219 } "NODE_NAME" } } { "DDS.v" "" { Text "E:/DDS/DDS.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.043 ns DDS:inst\|add\[9\]~221 11 COMB LAB_X12_Y6 2 " "Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 2.043 ns; Loc. = LAB_X12_Y6; Fanout = 2; COMB Node = 'DDS:inst\|add\[9\]~221'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { DDS:inst|add[8]~219 DDS:inst|add[9]~221 } "NODE_NAME" } } { "DDS.v" "" { Text "E:/DDS/DDS.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.107 ns) + CELL(0.086 ns) 2.236 ns DDS:inst\|add\[10\]~223 12 COMB LAB_X12_Y5 2 " "Info: 12: + IC(0.107 ns) + CELL(0.086 ns) = 2.236 ns; Loc. = LAB_X12_Y5; Fanout = 2; COMB Node = 'DDS:inst\|add\[10\]~223'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.193 ns" { DDS:inst|add[9]~221 DDS:inst|add[10]~223 } "NODE_NAME" } } { "DDS.v" "" { Text "E:/DDS/DDS.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.322 ns DDS:inst\|add\[11\]~225 13 COMB LAB_X12_Y5 2 " "Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 2.322 ns; Loc. = LAB_X12_Y5; Fanout = 2; COMB Node = 'DDS:inst\|add\[11\]~225'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { DDS:inst|add[10]~223 DDS:inst|add[11]~225 } "NODE_NAME" } } { "DDS.v" "" { Text "E:/DDS/DDS.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.408 ns DDS:inst\|add\[12\]~227 14 COMB LAB_X12_Y5 2 " "Info: 14: + IC(0.000 ns) + CELL(0.086 ns) = 2.408 ns; Loc. = LAB_X12_Y5; Fanout = 2; COMB Node = 'DDS:inst\|add\[12\]~227'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { DDS:inst|add[11]~225 DDS:inst|add[12]~227 } "NODE_NAME" } } { "DDS.v" "" { Text "E:/DDS/DDS.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.494 ns DDS:inst\|add\[13\]~229 15 COMB LAB_X12_Y5 2 " "Info: 15: + IC(0.000 ns