dds.fit.rpt

基于DDS原理的正弦信号发生器。用VERILOG语言实现

; Always Enable Input Buffers                                           ; Off                            ; Off                            ;
; Optimize Hold Timing                                                  ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                           ; Off                            ; Off                            ;
; Equivalent RAM and MLAB Paused Read Capabilities                      ; Care                           ; Care                           ;
; PowerPlay Power Optimization                                          ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                       ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                            ; On                             ; On                             ;
; Limit to One Fitting Attempt                                          ; Off                            ; Off                            ;
; Final Placement Optimizations                                         ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                           ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                         ; 1                              ; 1                              ;
; PCI I/O                                                               ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                                 ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                             ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                    ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/II GX/III Cyclone II/III Arria GX ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                     ; On                             ; On                             ;
; Auto Merge PLLs                                                       ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                                     ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Fitting        ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance    ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                          ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                           ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                             ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                                ; Off                            ; Off                            ;
; Fitter Effort                                                         ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                       ; Normal                         ; Normal                         ;
; Auto Global Clock                                                     ; On                             ; On                             ;
; Auto Global Register Control Signals                                  ; On                             ; On                             ;
; Stop After Congestion Map Generation                                  ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                     ; Off                            ; Off                            ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in E:/DDS/DDS.pin.


+---------------------------------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                                                     ;
+---------------------------------------------+-----------------------------------------------------+
; Resource                                    ; Usage                                               ;
+---------------------------------------------+-----------------------------------------------------+
; Total logic elements                        ; 31 / 33,216 ( < 1 % )                               ;
;     -- Combinational with no register       ; 10                                                  ;
;     -- Register only                        ; 0                                                   ;
;     -- Combinational with a register        ; 21                                                  ;
;                                             ;                                                     ;
; Logic element usage by number of LUT inputs ;                                                     ;
;     -- 4 input functions                    ; 0                                                   ;
;     -- 3 input functions                    ; 19                                                  ;
;     -- <=2 input functions                  ; 12                                                  ;
;     -- Register only                        ; 0                                                   ;
;                                             ;                                                     ;
; Logic elements by mode                      ;                                                     ;
;     -- normal mode                          ; 12                                                  ;
;     -- arithmetic mode                      ; 19                                                  ;
;                                             ;                                                     ;
; Total registers*                            ; 21 / 34,134 ( < 1 % )                               ;
;     -- Dedicated logic registers            ; 21 / 33,216 ( < 1 % )                               ;
;     -- I/O registers                        ; 0 / 918 ( 0 % )                                     ;
;                                             ;                                                     ;
; Total LABs:  partially or completely used   ; 3 / 2,076 ( < 1 % )                                 ;
; User inserted logic elements                ; 0                                                   ;
; Virtual pins                                ; 0                                                   ;
; I/O pins                                    ; 35 / 322 ( 11 % )                                   ;
;     -- Clock pins                           ; 1 / 8 ( 13 % )                                      ;
; Global signals                              ; 1                                                   ;
; M4Ks                                        ; 3 / 105 ( 3 % )                                     ;
; Total memory bits                           ; 10,240 / 483,840 ( 2 % )                            ;
; Total RAM block bits                        ; 13,824 / 483,840 ( 3 % )                            ;
; Embedded Multiplier 9-bit elements          ; 0 / 70 ( 0 % )                                      ;
; PLLs                                        ; 1 / 4 ( 25 % )                                      ;
; Global clocks                               ; 1 / 16 ( 6 % )                                      ;
; Average interconnect usage                  ; 0%                                                  ;
; Peak interconnect usage                     ; 0%                                                  ;
; Maximum fan-out node                        ; altpll0:inst1|altpll:altpll_component|_clk0~clkctrl ;
; Maximum fan-out                             ; 24                                                  ;
; Highest non-global fan-out signal           ; reset_n                                             ;
; Highest non-global fan-out                  ; 21                                                  ;
; Total fan-out                               ; 189                                                 ;
; Average fan-out                             ; 1.97                                                ;
+---------------------------------------------+-----------------------------------------------------+
*  Register count does not include registers inside RAM blocks or DSP blocks.



+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                         ;
+--------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name         ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+--------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+