📄 hkp3307.v.txt
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assign DATA[7:0] = cpu_dataout[7:0]; //cpu read out cpld data
//bctl data buffer control
assign CPU_245DIRn = ~RD_WRn ; //data buffer dirtecon control
assign CPU_245OEn = CSBn & CSAn & CSO0n & CSO1n; //data buffer enable control
//bctl interrupt interface
assign IRQAn = button_rstn_intn;
assign IRQBn = cardplug_intn;
//chips read and write control
assign FLASH_WEn = RD_WRn; //FLASH write enable
assign FLASH_OEn = ~RD_WRn; //FLASH output enable
assign FPGA_RW = RD_WRn; //FPGA read and write enable
assign NVRAM_WEn = RD_WRn; //NVRAM write enable
assign NVRAM_OEn = ~RD_WRn; //NVRAM output enable
assign HDLC_R_Wn = RD_WRn; //HDLC(485) read and write control
//############### SPI select ###################################################################################################//
always @( cpld_csn or RD_WRn or REGOUT) //local cpld registers out to cpu
begin
if (cpld_csn == 1'b0 )
if (RD_WRn == 1'b1 )
cpu_dataout[7:0] <= REGOUT[7:0];
else
cpu_dataout[7:0] <= 8'bzzzz_zzzz;
else
cpu_dataout[7:0] <= 8'bzzzz_zzzz;
end
always @(spi_select or SPI_SELn or SPI_CLK or SPI_MOSI or SWITCH1_SPI_MISO or E_SPI1_MISO or E_SPI2_MISO)
begin
case(spi_select[2:1])
2'b00:
begin
SWITCH1_SPI_SELn <= SPI_SELn;
SWITCH1_SPI_CLK <= SPI_CLK;
SWITCH1_SPI_MOSI <= SPI_MOSI;
SPI_MISO <= SWITCH1_SPI_MISO;
E_SPI1_SELn <= 1'b1;
E_SPI1_CLK <= 1'b1;
E_SPI1_MOSI <= 1'b0;
E_SPI2_SELn <= 1'b1;
E_SPI2_CLK <= 1'b1;
E_SPI2_MOSI <= 1'b0;
end
2'b01:
begin
E_SPI1_SELn <= SPI_SELn;
E_SPI1_CLK <= SPI_CLK;
E_SPI1_MOSI <= SPI_MOSI;
SPI_MISO <= E_SPI1_MISO;
SWITCH1_SPI_SELn<= 1'b1;
SWITCH1_SPI_CLK <= 1'b1;
SWITCH1_SPI_MOSI<= 1'b0;
E_SPI2_SELn <= 1'b1;
E_SPI2_CLK <= 1'b1;
E_SPI2_MOSI <= 1'b0;
end
2'b10:
begin
E_SPI2_SELn <= SPI_SELn;
E_SPI2_CLK <= SPI_CLK;
E_SPI2_MOSI <= SPI_MOSI;
SPI_MISO <= E_SPI2_MISO;
SWITCH1_SPI_SELn<= 1'b1;
SWITCH1_SPI_CLK <= 1'b1;
SWITCH1_SPI_MOSI<= 1'b0;
E_SPI1_SELn <= 1'b1;
E_SPI1_CLK <= 1'b1;
E_SPI1_MOSI <= 1'b0;
end
default:
begin
E_SPI2_SELn <= 1'b1;
E_SPI2_CLK <= 1'b1;
E_SPI2_MOSI <= 1'b0;
SWITCH1_SPI_SELn<= 1'b1;
SWITCH1_SPI_CLK <= 1'b1;
SWITCH1_SPI_MOSI<= 1'b0;
E_SPI1_SELn <= 1'b1;
E_SPI1_CLK <= 1'b1;
E_SPI1_MOSI <= 1'b0;
end
endcase
end
//############### OAM status control #######################################################################//
//ACT[1:0]==2'b11---- Not ready
//ACT[1:0]==2'b01---- Ready but standby
//ACT[1:0]==2'b10---- Ready and active
//ACT[1:0]==2'b00---- Super master,Active overwrite "10"
always @(OAM_ACT or OAMs_ACT)
begin
case({OAM_ACT[1:0],OAMs_ACT[1:0]})
4'b10_11, //mine oam is "Ready and active" and mate oam is "Not ready"
4'b10_01, //mine oam is "Ready and active" and mate oam is "Ready but standby"
4'b00_11, //mine oam is "Super master" and mate oam is "Not ready"
4'b00_01, //mine oam is "Super master" and mate oam is "Ready but standby"
4'b00_10: //mine oam is "Super master" and mate oam is "Ready and active"
begin
BK_MASTER_CTLn <= 1'b0; //Open backplane bus
E_RESERVEOUT[4] <= 1'b0; //master or slave indicator
end
default:
begin
BK_MASTER_CTLn <= 1'b1; //Close backplane bus
E_RESERVEOUT[4] <= 1'b1;
end
endcase
end
//backplane buffer enable
assign BK_BUFFER_ENn[2:0] = 3'b000;
assign OAM1_ACTn = E_RESERVEOUT[4];
//############### Produce 128K and 256K clock #######################################################################//
always @(posedge CPUCLK or negedge rstn)
begin
if(rstn==1'b0)
cpuclk_cnt <= 8'h00;
else
cpuclk_cnt <= cpuclk_cnt + 1'b1;
end
always @(posedge CPUCLK or negedge rstn)
begin
if(rstn==1'b0)
clk128k <= 1'b0;
else if (cpuclk_cnt==8'b1111_1111)
clk128k <= ~clk128k;
end
always @(posedge CPUCLK or negedge rstn)
begin
if(rstn==1'b0)
clk256k <= 1'b0;
else if (cpuclk_cnt[6:0]==7'b111_1111)
clk256k <= ~clk256k;
end
//############### Button reset control #####################################################################################//
always @(posedge clk128k or negedge rstn)
begin //signal filter
if (rstn==1'b0)
swtn_d <= 1'b1;
else
swtn_d <= Button_RSTn;
end
assign button_rstn_intn = swtn_d | (~button_rstn_intn_mask);
always @(posedge clk128k or negedge CPU_WATCHDOG_RSTn)
begin //detect posedge of Button_RSTn
if (CPU_WATCHDOG_RSTn==1'b0)
swtn_cnt_en <= 1'b0;
else if ( (~swtn_d) & Button_RSTn)
swtn_cnt_en <= 1'b1;
end
always @(posedge clk128k or negedge CPU_WATCHDOG_RSTn)
begin
if (CPU_WATCHDOG_RSTn==1'b0)
swtn_cnt[18:0] <= 19'h0_0000;
else if(swtn_cnt_en==1'b1)
swtn_cnt[18:0] <= swtn_cnt[18:0] + 1'b1;
end
always @(negedge CPUCLK or negedge CPU_WATCHDOG_RSTn )
begin
if (CPU_WATCHDOG_RSTn ==1'b0)
button_rstn_reg <= 1'b1;
else if (swtn_cnt==19'h3_e800)
button_rstn_reg <= 1'b0;
end
assign CPU_MR_RSTn = button_rstn_reg & oam_rstn;
//############# Reset control between OAM and mate OAM #####################################################################//
//Receive Serial mate OAM to OAM reset pulse
always @(posedge clk256k or negedge CPU_WATCHDOG_RSTn)
begin
if(CPU_WATCHDOG_RSTn==1'b0)
oams_oam_rstn_dl <= 1'b0;
else
oams_oam_rstn_dl <=E_RESERVEIN[3];
end
always @(posedge clk256k or negedge CPU_WATCHDOG_RSTn)
begin //When detect the first negedge of OAMs_OAM_RSTn, produce 16 clk256k clock enable signal
if(CPU_WATCHDOG_RSTn==1'b0)
rxpulse_cnt <= 4'b0000;
else if(oams_oam_rstn_dl&(~E_RESERVEIN[3]))
rxpulse_cnt[3:0] <= rxpulse_cnt + 1'b1;
end
always @(posedge clk256k or negedge CPU_WATCHDOG_RSTn)
begin //if receive 3 negedge of OAMs_OAM_RSTn during 16 clk256k clocks, produce 1 clk256k reset pulse
if (CPU_WATCHDOG_RSTn == 1'b0)
oam_rstn <= 1'b1;
else if (rxpulse_cnt==4'b0110)
oam_rstn <= 1'b0;
end
//Send out 64KHz pulse, used to reset mate OAM
always @(posedge clk128k or negedge rstn)
begin
if(rstn==1'b0)
oams_rstn_dl <= 1'b1;
else
oams_rstn_dl <= OAM_OAMs_RSTn;
end
always @(posedge clk128k or negedge rstn)
begin
if(rstn==1'b0)
oams_rstn_en <= 1'b0;
else if (oams_rstn_dl & (~OAM_OAMs_RSTn)& (txpulse_cnt==4'b0000))
oams_rstn_en <= 1'b1;
else if (txpulse_cnt==4'b1110)
oams_rstn_en <= 1'b0;
end
always @(posedge clk128k or negedge rstn)
begin
if(rstn==1'b0)
begin
E_RESERVEOUT[3] <= 1'b1;
txpulse_cnt[3:0]<= 4'b0000;
end
else if(oams_rstn_en==1'b1)
begin
E_RESERVEOUT[3] <= ~E_RESERVEOUT[3];
txpulse_cnt <= txpulse_cnt + 1'b1;
end
else
begin
E_RESERVEOUT[3] <= 1'b1;
txpulse_cnt[3:0]<= 4'b0000;
end
end
//############### OAM card plug process #####################################################################################//
always @(posedge clk128k or negedge rstn)
begin
if(rstn == 1'b0)
cardplugn_d <= 1'b0;
else
cardplugn_d <= Card_PLUGn[1] | Card_PLUGn[0];
end
always @(posedge clk128k or negedge rstn)
begin
if(rstn == 1'b0)
cardplug_intn <= 1'b1;
else if (((~cardplugn_d) & (Card_PLUGn[1] | Card_PLUGn[0])) & cardpulg_intn_mask)
cardplug_intn <= 1'b0;
else
cardplug_intn <= 1'b1;
end
//############### OAM Watchdog used as a low frequency clock #####################################################################################//
assign WATCHDOG_MR = 1'b1;
//############### ShelfIO FE ports status dectect ################################################################################//
always @(posedge SWITCH0_LED_CLK or negedge SWITCH0_RESET)
begin
if(SWITCH0_RESET==1'b0)
cnt128[6:0] <= 7'b000_0000;
else if(cnt128[6:0]==7'b111_0011)
cnt128[6:0] <= 7'b000_0000;
else
cnt128[6:0] <= cnt128[6:0] + 1'b1;
end
always @(posedge SWITCH0_LED_CLK or negedge SWITCH0_RESET)
begin //should config switch0 LEDMODE[2:0]==3'b010
if(SWITCH0_RESET==1'b0)
begin
E_RES_LED[1] <= 1'b0;
E_RES_LED[0] <= 1'b0;
SWITCH0_LED_TX <= 1'b1;
SWITCH0_LINK <= 1'b1;
end
else if(cnt128[6:0]==7'b000_1010)
E_RES_LED[1] <= SWITCH0_LED_DATA;
else if(cnt128[6:0]==7'b000_1011)
E_RES_LED[0] <=SWITCH0_LED_DATA;
else if(cnt128[6:0]==7'b011_1010)
SWITCH0_LED_TX <=SWITCH0_LED_DATA;
else if(cnt128[6:0]==7'b011_1011)
SWITCH0_LINK <=SWITCH0_LED_DATA;
end
assign OAM_CONS_FE_LINKn_2 =1'b1;
assign OAM_CONS_FE_ACTn_2 =1'b1;
//############### Others ###################################################################################################//
assign HDLC_TXEN0 = ~HDLC_TXD0;
assign HDLC_TXEN1 = ~HDLC_TXD1;
DECODE U0_DECODE
(
.HADDR(HADDR),
.CSAn(CSAn),
.CSBn(CSBn),
.CSO0n(CSO0n),
.CSO1n(CSO1n),
.FLASH0_CSn(FLASH0_CSn),
.FLASH1_CSn(FLASH1_CSn),
.NVRAM_RAM_CEn(NVRAM_RAM_CEn),
.NVRAM_RTC_CSn(NVRAM_RTC_CSn),
.HDLC_CSn(HDLC_CSn),
.HDLC_DSn(HDLC_DSn),
.CPLD_CSn(cpld_csn),
.FPGA_CSn(FPGA_CSn),
.CPUCLK(CPUCLK),
.PWR_RSTn(rstn)
);
CPU_REG U1_CPU_REG
(
//CPU interface
.E_IOOUT(E_IOOUT),
.E_IOIN(E_IOIN),
.PWR_RSTn(rstn),
.CPUCLK(CPUCLK),
.CPLD_CSn(cpld_csn),
.RD_WRn(RD_WRn),
.ADDR(ADDR),
.CPU_DATAIN(cpu_datain),
.REGOUT(REGOUT),
.IRQCn(IRQCn),
.BK_SLOTID(BK_SLOTID),
.BK_SHELFID(BK_SHELFID),
.BK_VER(BK_VER),
.PCB_VER(PCB_VER),
.SW(SW),
//panel LED interface
.LED_R(LED_R),
.LED_G(LED_G),
.LED_YA(LED_YA),
.LED_YK(LED_YK),
//cards online
.OAMs_ONLINEn(OAMs_ONLINEn),
.FAN_ONLINEn(FAN_ONLINEn),
.PWIN_ONLINEn(PWIN_ONLINEn),
.CONSOLE_ONLINEn(CONSOLE_ONLINEn),
.INVENTORY_ONLINEn(INVENTORY_ONLINEn),
.CLK_ONLINEn(CLK_ONLINEn),
.IO_ONLINEn(IO_ONLINEn),
.LINECARD_ONLINEn(LINECARD_ONLINEn),
//OAM active and standby status interface
.OAMs_HeartBeat(OAMs_HeartBeat),
.OAMs_ACT(OAMs_ACT),
.OAM_ACT(OAM_ACT),
.OAM_WATCHDOG(OAM_WATCHDOG),
//chip reset interface
.FLASH0_RSTn(FLASH0_RSTn),
.FLASH1_RSTn(FLASH1_RSTn),
.NVRAM_RSTn(NVRAM_RSTn),
.HDLC_RST(HDLC_RST),
.SWITCH0_RESET(SWITCH0_RESET),
//interrupt
.NVRAM_RTC_IRQn(NVRAM_RTC_IRQn),
.HDLC_IRQn(HDLC_IRQn),
.TMEPER_IRQn(TMEPER_IRQn),
//FLASH
.FLASH0_VPn(FLASH0_VPn),
.FLASH1_VPn(FLASH1_VPn),
//FPGA
.FPGA_DIN(FPGA_DIN),
.FPGA_DCLK(FPGA_DCLK),
.FPGA_PROGn(FPGA_PROGn),
.FPGA_CONF_DONE(FPGA_CONF_DONE),
.FPGA_CLK(FPGA_CLK),
.FPGA_CPLD_RSV(FPGA_CPLD_RSV),
.CPLD_FPGA_RSV(CPLD_FPGA_RSV),
.FPGA_INT(FPGA_INT),
.FPGA_RSTn(FPGA_RSTn),
.FPGA_SLOT0_INT(FPGA_SLOT0_INT),
.FPGA_SLOT1_INT(FPGA_SLOT1_INT),
.FPGA_SLOT2_INT(FPGA_SLOT2_INT),
//SHELF IO
.ACO(ACO),
.CR_ALM(CR_ALM),
.MJ_ALM(MJ_ALM),
.MI_ALM(MI_ALM),
.E_FAN_ALM(E_FAN_ALM),
.E_PWIN1_ALM(E_PWIN1_ALM),
.E_PWIN2_ALM(E_PWIN2_ALM),
.E_CLK2_STATUS(E_CLK2_STATUS),
.E_CLK1_STATUS(E_CLK1_STATUS),
.E_LED(E_LED),
//Buzzer
.BUZZER(BUZZER),
//Heart beat to mate OAM
.WATCHDOG_RSTn(WATCHDOG_RSTn),
//SPI bus select
.SPI_SELECT(spi_select),
//interrup masks
.BUTTON_RSTn_INTn_MASK(button_rstn_intn_mask),
.CARDPLUG_INTn_MASK(cardpulg_intn_mask),
.Card_PLUGn(Card_PLUGn),
.CPU_WATCHDOG_RSTn(CPU_WATCHDOG_RSTn),
.CLK128K(clk128k),
.IIC_EN1(IIC_EN1),
.IIC_EN2(IIC_EN2),
.IIC_EN3(IIC_EN3),
.E_RESERVEIN(E_RESERVEIN),
.OAM1_ACTn(OAM1_ACTn),
.OAM_OAMs_RSTn(OAM_OAMs_RSTn),
.CONS_RUN(CONS_RUN)
);
// CODEs END HERE
endmodule
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