📄 hkp3307.v.txt
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//******************************************************************************
//
// Copyright(c) 2008, UTstarcom Technologies Co., Ltd.
// All rights reserved
//
// Project Name : HKP3307
// Filename : HKP3307.v
// designer : Wang Jianping
// EMail : jpwang@utstar.com
// Date : 2008/05/05
// Version : 1.1.0.0
//
// MODULE Name : HKP3307
// description : The top level design
// Called by : This is top module
//
// Modification History
// -----------------------------------------------------------------------------
// 2008-05-05 Wang Jianping Revision according review
//
//******************************************************************************
//MACRO DEFINITIONs BEGIN HERE
`timescale 1ns/10ps
//MACRO DEFINITIONs END HERE
module HKP3307
(
//CPLD Internal CPU Interface
PWR_RSTn, //from max708 : power on reset
CPLD_RSTn, //from bctl : CPLD hardware reset after VME load
DATA, //from bctl : cpu_data7~cpu_data0, CPU read or write data
ADDR, //from bctl : cpu_addr7~cpu_addr0, CPU low address bit
HADDR, //from bctl : cpu_addr24~cpu_addr20, CPU high bit address used for address decode
CSAn, //from bctl : cpu_cs4(32bit), base address--0xa0000000
CSBn, //from bctl : cpu_cs5(32bit), base address--0xb0000000
CSO0n, //from bctl : cpu_cs2(16bit), base address--0xc0000000
CSO1n, //from bctl : cpu_cs3(8bit) , base address--0xd0000000
RD_WRn, //from bctl : cpu read and write control signal, high--read,low--write
DRDYn, //to bctl : cpu data ready acknowledge singal, reserved for future use
CPUCLK, //from bctl : cpu clock--66MHz
IRQAn, //to bctl : cpu interrupt--IRQ3, used for button reset interrupt
IRQBn, //to bctl : cpu interrupt--IRQ4, used for OAM card plug button interrupt
IRQCn, //to bctl : cpu interrupt--IRQ5, used for other interrupts
CPU_245OEn, //to bctl : data buffer ouput enable singal
CPU_245DIRn, //to bctl : data buffer direction singal
CPU_MR_RSTn, //to bctl : watchdog chip manual reset control signal
CPU_WATCHDOG_RSTn, //from bctl : watchdog chip reset signal
IOA, //from bctl : IO reserved for future use
IOB, //from bctl : IO reserved for future use
IOC, //from bctl : IO reserved for future use
IOD, //from bctl : IO reserved for future use
//Card Online
OAMs_ONLINEn, //from mate OAM card : card online signal
FAN_ONLINEn, //from FAN cards : card online signals
PWIN_ONLINEn, //from PWIN cards : card online signals
CONSOLE_ONLINEn, //from CONSOLE card : card online signal
INVENTORY_ONLINEn, //from INV card : card online signal
CLK_ONLINEn, //from CLK_ONLINEn card : only for TN715
IO_ONLINEn, //from IO cards : card online signals
LINECARD_ONLINEn, //from LINE card : card online signalS
//OAM Master and slave control
OAMs_ACT, //from mate OAM card: status indication signal:
//OAMs_ACT[1:0]==2'b11---- Not ready
//OAMs_ACT[1:0]==2'b01---- Ready but standby
//OAMs_ACT[1:0]==2'b10---- Ready active
//OAMs_ACT[1:0]==2'b00---- Super master,Active overwrite "10"
OAMs_HeartBeat, //from mate OAM card: heart beat indication signal
OAM_ACT, //to mate OAM card: status indication signal:
//OAM_ACT[1:0]==2'b11---- Not ready
//OAM_ACT[1:0]==2'b01---- Ready but standby
//OAM_ACT[1:0]==2'b10---- Ready active
//OAM_ACT[1:0]==2'b00---- Super master,Active overwrite "10"
OAM_WATCHDOG, //to OAMs card : heart beat indication signal
//BK information
BK_SLOTID, //from backplane : slot id[3:1]
BK_SHELFID, //from backplane : BK_SHELFID[2:1]
BK_VER, //from backplane : pcb version
//BK buffer
BK_MASTER_CTLn, //OAM backplane buffer active/standby control signal
BK_BUFFER_ENn, //OAM backplane buffer enable signal
//FLASH
FLASH_WEn, //flash chip write enable signal
FLASH_OEn, //flash chip output enable signal
FLASH0_CSn, //flash0 chip select signal
FLASH1_CSn, //flash1 chip select signal
FLASH0_VPn, //flash0 first sector write protect control signal
FLASH1_VPn, //flash1 first sector write protect control signal
FLASH0_RSTn, //flash0 chip reset control signal
FLASH1_RSTn, //flash1 chip reset control signal
//NVRAM
NVRAM_WEn, //NVRAM write enable signal
NVRAM_OEn, //NVRAM output enable signal
NVRAM_RAM_CEn, //NVRAM RAM space select signal
NVRAM_RTC_CSn, //NVRAM RTC space select signal
NVRAM_RTC_IRQn, //NVRAM RTC IRQn
NVRAM_RSTn, //NVRAM reset signal
//HDLC
HDLC_R_Wn, //HDLC(485) read and write control signal: high--read, low--write
HDLC_CSn, //HDLC(485) chip select signal
HDLC_DSn, //HDLC(485) data strobe signal
HDLC_IRQn, //HDLC(485) IRQn
HDLC_RST, //HDLC(485) chip reset signal
HDLC_TXD0, //HDLC(485) TXD0 signal
HDLC_TXD1, //HDLC(485) TXD1 signal
HDLC_TXEN0, //485 driver TXD0 enable signal
HDLC_TXEN1, //485 driver TXD1 enable signal
HDLC_DI0, //485 driver TX0 enable signal
HDLC_DI1, //485 driver TX1 enable signal
//IIC
IIC_EN1, //IIC enable signal-PWIN,inv etc
IIC_EN2, //IIC enable signal-line card
IIC_EN3, //IIC enable signal
//Temperature
TMEPER_IRQn, //temperature inspect IRQn
//Switch
SWITCH0_RESET, //switch reset signal
SPI_SELn, //from bctl: SPI bus device select signal
SPI_CLK, //from bctl: SPI_CLK
SPI_MOSI, //from bctl: SPI_MOSI
SPI_MISO, //from bctl: SPI_MISO
SWITCH1_SPI_SELn, //switch device select signal
SWITCH1_SPI_CLK, //switch SPI_CLK
SWITCH1_SPI_MOSI, //switch SPI_MOSI
SWITCH1_SPI_MISO, //switch SPI_MISO
SWITCH0_LED_CLK, //switch LED intferface clock signal
SWITCH0_LED_DATA, //switch LED intferface data signal
SWITCH0_LED_TX, //oam panel Fe ACT control
SWITCH0_LINK, //oam panel Fe LINK control
//FPGA
FPGA_DIN, //FPGA soft programe data input signal
FPGA_DCLK, //FPGA soft programe clock input signal
FPGA_PROGn, //FPGA soft programe control signal
FPGA_CONF_DONE, //FPGA confige done indication signal
FPGA_CLK, //FPGA to CPLD CLK input
FPGA_INT, //FPGA interrupt
FPGA_CSn, //FPGA chip select signal
FPGA_RW, //FPGA read and write signal
FPGA_RSTn, //FPGA reset control signal
FPGA_SLOT0_INT, //Reserved signal
FPGA_SLOT1_INT, //Reserved signal
FPGA_SLOT2_INT, //Reserved signal
FPGA_CPLD_RSV, //Reserved signal
CPLD_FPGA_RSV, //Reserved signal
//Others
Card_PLUGn, //card plug indication
PCB_VER, //PCB version
SW, //switch button signal
LED_R, //panel red led control, low--light
LED_G, //panel green led control, low--light
LED_YA, //panel green/yellow led control
LED_YK, //panel green/yellow led control:
//{LED_YA,LED_YK}=2'b01---- green
//{LED_YA,LED_YK}=2'b10---- yellow
//{LED_YA,LED_YK}=2'b00---- no light
//{LED_YA,LED_YK}=2'b11---- no light
Button_RSTn, //from panel reset button, board reset signal
WATCHDOG_MR, //watchdog manual reset signal
WATCHDOG_RSTn, //watchdog reset signal
BUZZER, //buzzer control signal
E_RESERVEIN, //bit4:OAM2_ACTn;bit3:OAM2_OAM1_RSTn;bit2:PPC2_ACTn;bit1:PPC1_ACTn
E_RESERVEOUT, //bit4:OAM1_ACTn;bit3:OAM1_OAM2_RSTn
OAM_CONS_FE_ACTn_2, //to console reserved for future
OAM_CONS_FE_LINKn_2, //to console reserved for future
E_IOIN, //IO card on-off 4 channel input
E_IOOUT, //IO card on-off 4 channel output
CR_ALM, //console, Cr_alm output of local system
MJ_ALM, //console, Mj_alm output of local system
MI_ALM, //console, Mi_alm output of local system
ACO, //console, local system's alm-clear signal input
E_RES_LED, //E_RES_LED[1]---console Fe ACT signal
//E_RES_LED[0]---console Fe LINK signal
CONS_RUN, //console running led control
E_SPI1_SELn, //to bkp SPI reserved for future
E_SPI1_CLK,
E_SPI1_MOSI,
E_SPI1_MISO,
E_SPI2_SELn, //to bkp SPI reserved for future
E_SPI2_CLK,
E_SPI2_MOSI,
E_SPI2_MISO,
E_FAN_ALM, //fan alm-low:alm;high:no alm
E_PWIN1_ALM, //pwin1 alm-low:no alm;high:alm
E_PWIN2_ALM, //pwin2 alm-low:no alm;high:alm
E_CLK2_STATUS, //only for TN715;
E_CLK1_STATUS, //only for TN715;
E_LED //test led;
);
//***************************************************
// MODULE's IO DECLARATIONs BEGIN HERE
//***************************************************
//CPLD Internal CPU Interface
input PWR_RSTn;
input CPLD_RSTn;
inout [7:0]DATA;
input [5:0]ADDR;
input [24:20]HADDR;
input CSAn;
input CSBn;
input CSO0n;
input CSO1n;
input RD_WRn;
input DRDYn;
input CPUCLK;
output IRQAn;
output IRQBn;
output IRQCn;
output CPU_245OEn;
output CPU_245DIRn;
output CPU_MR_RSTn;
input CPU_WATCHDOG_RSTn;
input IOA;
input IOB;
input IOC;
input IOD;
//Cards Online
input OAMs_ONLINEn;
input FAN_ONLINEn;
input [1:0] PWIN_ONLINEn;
input CONSOLE_ONLINEn;
input INVENTORY_ONLINEn;
input [1:0] CLK_ONLINEn;
input IO_ONLINEn;
input [28:10] LINECARD_ONLINEn;
input [1:0] FPGA_CPLD_RSV;
output [1:0] CPLD_FPGA_RSV;
//OAM Master and slave control
input [1:0]OAMs_ACT;
input OAMs_HeartBeat;
output [1:0]OAM_ACT;
output OAM_WATCHDOG;
//BK
input [3:1]BK_SLOTID;
input [2:1]BK_SHELFID;
input [3:0]BK_VER;
//BK buffer
output BK_MASTER_CTLn;
output [2:0]BK_BUFFER_ENn;
//FLASH
output FLASH_WEn;
output FLASH_OEn;
output FLASH0_CSn;
output FLASH1_CSn;
output FLASH0_VPn;
output FLASH1_VPn;
output FLASH0_RSTn;
output FLASH1_RSTn;
//NVRAM
output NVRAM_WEn;
output NVRAM_OEn;
output NVRAM_RAM_CEn;
output NVRAM_RTC_CSn;
input NVRAM_RTC_IRQn;
input NVRAM_RSTn;
//HDLC
output HDLC_R_Wn;
output HDLC_CSn;
output HDLC_DSn;
input HDLC_IRQn;
output HDLC_RST;
input HDLC_TXD0;
input HDLC_TXD1;
output HDLC_TXEN0;
output HDLC_TXEN1;
output HDLC_DI0;
output HDLC_DI1;
output IIC_EN1;
output IIC_EN2;
output IIC_EN3;
//Temperature
input TMEPER_IRQn;
//Switch
input SPI_SELn;
input SPI_CLK;
input SPI_MOSI;
output SPI_MISO;
output SWITCH1_SPI_SELn;
output SWITCH1_SPI_CLK;
output SWITCH1_SPI_MOSI;
input SWITCH1_SPI_MISO;
input SWITCH0_LED_CLK;
input SWITCH0_LED_DATA;
output SWITCH0_RESET;
output SWITCH0_LED_TX;
output SWITCH0_LINK;
//Fpga
output FPGA_DIN;
output FPGA_DCLK;
output FPGA_PROGn;
input FPGA_CONF_DONE;
input FPGA_CLK;
input FPGA_INT;
output FPGA_CSn;
output FPGA_RW;
output FPGA_RSTn;
input FPGA_SLOT0_INT;
input FPGA_SLOT1_INT;
input FPGA_SLOT2_INT;
input [1:0]Card_PLUGn;
//Others
input [3:0]PCB_VER;
input [3:0]SW;
output [3:0]E_IOOUT;
output LED_R;
output LED_G;
output LED_YA;
output LED_YK;
input Button_RSTn;
output WATCHDOG_MR;
input WATCHDOG_RSTn;
output BUZZER;
input [4:1]E_RESERVEIN;
output [4:3]E_RESERVEOUT;
output OAM_CONS_FE_ACTn_2;
output OAM_CONS_FE_LINKn_2;
input [3:0]E_IOIN;
output CR_ALM,
output MJ_ALM,
output MI_ALM,
input ACO,
output [1:0]E_RES_LED;
output E_SPI1_SELn;
output E_SPI1_CLK;
output E_SPI1_MOSI;
input E_SPI1_MISO;
output E_SPI2_SELn;
output E_SPI2_CLK;
output E_SPI2_MOSI;
input E_SPI2_MISO;
input E_FAN_ALM;
input E_PWIN1_ALM;
input E_PWIN2_ALM;
input [2:1]E_CLK2_STATUS;
input [2:1]E_CLK1_STATUS;
output E_LED;
output CONS_RUN;
//***************************************************
// INTERNAL SIGNAL DECLARATIONs BEGIN HERE
//***************************************************
wire [2:1]spi_select;
wire [4:1]E_RESERVEIN;
reg [1:0]E_RES_LED;
wire [3:0]E_IOIN;
wire [3:0]E_IOOUT;
wire SWITCH0_RESET;
reg BK_MASTER_CTLn;
reg SWITCH1_SPI_SELn;
reg SWITCH1_SPI_CLK;
reg SWITCH1_SPI_MOSI;
reg SPI_MISO;
reg E_SPI1_SELn;
reg E_SPI1_CLK;
reg E_SPI1_MOSI;
reg [4:3]E_RESERVEOUT;
wire OAM_CONS_FE_ACTn_2;
wire OAM_CONS_FE_LINKn_2;
reg E_SPI2_SELn;
reg E_SPI2_CLK;
reg E_SPI2_MOSI;
reg [7:0]cpuclk_cnt; //CPUCLK counter, used to produce 128K clock
reg clk256k;
reg clk128k;
reg swtn_d; //Button_RSTn delay
reg swtn_cnt_en; //Button_RSTn counter enable
reg [18:0]swtn_cnt; //Button_RSTn counter enable
wire button_rstn_intn; //Button_RSTn interrupt
wire button_rstn_intn_mask; //Button_RSTn interrupt mask
reg button_rstn_reg; //use to buffer button reset to cpu
reg SWITCH0_LED_TX;
reg SWITCH0_LINK;
reg [7:0]cpu_dataout; //register data out to cpu
wire [7:0]cpu_datain; //cpu data into register
wire [7:0]REGOUT;
reg cardplugn_d; //Card_PLUGn delay
reg cardplug_intn; //Card_PLUGn interrupt
wire cardpulg_intn_mask; //Card_PLUGn interrupt mask
wire OAM1_ACTn;
reg [6:0]cnt128; //switch0 FE port LED interface clock counter
wire OAM_OAMs_RSTn;
//the signal used to apply the resets between OAM and mate OAM
wire cpld_csn;
reg oams_oam_rstn_dl;
reg [3:0]rxpulse_cnt;
reg oam_rstn;
reg oams_rstn_dl;
reg oams_rstn_en;
reg [3:0]txpulse_cnt;
wire CONS_RUN;
// INTERNAL SIGNAL DECLARATIONs END HERE
//***************************************************
// CODEs BEGIN HERE
//***************************************************
GSR GSR_INST (.GSR (CPLD_RSTn));
assign rstn = PWR_RSTn & CPLD_RSTn;
assign HDLC_DI0=1'b0; //485 driver TXD0 enable signal
assign HDLC_DI1=1'b0; //485 driver TXD1 enable signal
//############### CPU data interface #####################################################################################//
assign cpu_datain[7:0] = DATA[7:0]; //cpu write into data_in wire
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